"Specifications"
Specifications
Initial specifications for this design step
The noise specifications at the beginning of this design step are listed below.
design specification
Table design specification symbol | description | value | units |
$C_{i}$ | Required value of integrator capacitor | $1.59 \cdot 10^{-9}$ | $\mathrm{F}$ |
$I_{fb}$ | Maximum peak-peak current through feedback network | $4.022 \cdot 10^{-5}$ | $\mathrm{A}$ |
$L_{Mp}$ | Selected length input stage NMOS | $1.0 \cdot 10^{-6}$ | $\mathrm{m}$ |
$R_{i}$ | Selected value of integrator resistor | $1.0 \cdot 10^{4}$ | $\mathrm{\Omega}$ |
$Ri_{max}$ | Max. value of integrator resistor | $1.0 \cdot 10^{4}$ | $\mathrm{\Omega}$ |
$SRCnoise$ | DIN A weighted RMS output noise, source + termination | $1.819 \cdot 10^{-6}$ | $\mathrm{V}$ |
$c_{issP}$ | Selected input capacitance NMOS | $1.205 \cdot 10^{-12}$ | $\mathrm{F}$ |
$c_{iss costs minP}$ | Required c_iss for minimum costs | $1.205 \cdot 10^{-12}$ | $\mathrm{F}$ |
$c_{iss g m minP}$ | Required c_iss at g_m_min | $7.23 \cdot 10^{-10}$ | $\mathrm{F}$ |
$g_{mP}$ | Selected transconductance input stage NMOS | $3.089 \cdot 10^{-5}$ | $\mathrm{\mathtt{\text{S}}}$ |
$g_{m costs minP}$ | g_m for minimum costs | $3.089 \cdot 10^{-5}$ | $\mathrm{\mathtt{\text{S}}}$ |
$g_{m minP}$ | Minimum transconductance input stage NMOS | $1.54 \cdot 10^{-5}$ | $\mathrm{\mathtt{\text{S}}}$ |
performance specification
Table performance specification symbol | description | value | units |
$L_{s}$ | Source inductance | $0.12$ | $\mathrm{H}$ |
$R_{s}$ | Source resistance | $875$ | $\mathrm{\Omega}$ |
$R_{t}$ | Termination resistance | $7547.0$ | $\mathrm{H}$ |
$V_{onoise}$ | DIN A weighted output voltage noise | $1.191 \cdot 10^{-5}$ | $\mathrm{V}$ |
$Vi_{ADC}$ | Peak-peak input voltage ADC | $0.9$ | $\mathrm{V}$ |
$Vi_{pp}$ | Maximum peak-peak input voltage | $0.3215$ | |
$f_{fp}$ | Maximum full-power frequency | $5000$ | $\mathrm{Hz}$ |
$f_{max}$ | -3dB low-pass cut-off frequency | $6000$ | $\mathrm{Hz}$ |
$f_{min}$ | -3dB high-pass cut-off frequency | $300$ | $\mathrm{Hz}$ |
$\tau_{i}$ | Integration time constant | $1.59 \cdot 10^{-5}$ | $\mathrm{s}$ |
achievements specification
Table achievements specification symbol | description | value | units |
$V_{onoise gmCissP}$ | DIN A weighted RMS output noise with g_m, and c_iss | $1.308 \cdot 10^{-5}$ | $\mathrm{V}$ |
budgets specification
Table budgets specification symbol | description | value | units |
$n_{Ri}$ | Max. contribution of R_i to the DIN A weighted squared output noise | $0.25$ | |
$n_{SRC}$ | Relative contribution of source to squared output noise | $0.02333$ | |
Updated specifications
After finishing this design step the updated specifications are:
design specification
Table design specification symbol | description | value | units |
$C_{i}$ | Required value of integrator capacitor | $1.59 \cdot 10^{-9}$ | $\mathrm{F}$ |
$IC_{Mp}$ | Inversion coefficient input stage PMOS | $0.01867$ | |
$ID_{Mp}$ | Operating current input stage PMOS | $-1.082 \cdot 10^{-6}$ | $\mathrm{A}$ |
$I_{fb}$ | Maximum peak-peak current through feedback network | $4.022 \cdot 10^{-5}$ | $\mathrm{A}$ |
$L_{Mp}$ | Selected length input stage NMOS | $1.0 \cdot 10^{-6}$ | $\mathrm{m}$ |
$M_{Mp}$ | Number of fingers input stage PMOS | $42$ | |
$R_{i}$ | Selected value of integrator resistor | $1.0 \cdot 10^{4}$ | $\mathrm{\Omega}$ |
$Ri_{max}$ | Max. value of integrator resistor | $1.0 \cdot 10^{4}$ | $\mathrm{\Omega}$ |
$SRCnoise$ | DIN A weighted RMS output noise, source + termination | $1.819 \cdot 10^{-6}$ | $\mathrm{V}$ |
$W_{F Mp}$ | Finger width input stage PMOS | $1.0 \cdot 10^{-5}$ | $\mathrm{m}$ |
$W_{Mp}$ | Selected width input stage PMOS | $0.00042$ | $\mathrm{m}$ |
$c_{issP}$ | Selected input capacitance NMOS | $1.205 \cdot 10^{-12}$ | $\mathrm{F}$ |
$c_{iss Mp}$ | Obtained input capacitance input stage PMOS | $1.181 \cdot 10^{-12}$ | $\mathrm{F}$ |
$c_{iss costs minP}$ | Required c_iss for minimum costs | $1.205 \cdot 10^{-12}$ | $\mathrm{F}$ |
$c_{iss g m minP}$ | Required c_iss at g_m_min | $7.23 \cdot 10^{-10}$ | $\mathrm{F}$ |
$g_{mP}$ | Selected transconductance input stage NMOS | $3.089 \cdot 10^{-5}$ | $\mathrm{\mathtt{\text{S}}}$ |
$g_{m Mp}$ | Obtained transconductance input stage PMOS | $3.089 \cdot 10^{-5}$ | $\mathrm{\mathtt{\text{S}}}$ |
$g_{m costs minP}$ | g_m for minimum costs | $3.089 \cdot 10^{-5}$ | $\mathrm{\mathtt{\text{S}}}$ |
$g_{m minP}$ | Minimum transconductance input stage NMOS | $1.54 \cdot 10^{-5}$ | $\mathrm{\mathtt{\text{S}}}$ |
performance specification
Table performance specification symbol | description | value | units |
$L_{s}$ | Source inductance | $0.12$ | $\mathrm{H}$ |
$R_{s}$ | Source resistance | $875$ | $\mathrm{\Omega}$ |
$R_{t}$ | Termination resistance | $7547.0$ | $\mathrm{H}$ |
$V_{onoise}$ | DIN A weighted output voltage noise | $1.191 \cdot 10^{-5}$ | $\mathrm{V}$ |
$Vi_{ADC}$ | Peak-peak input voltage ADC | $0.9$ | $\mathrm{V}$ |
$Vi_{pp}$ | Maximum peak-peak input voltage | $0.3215$ | |
$f_{fp}$ | Maximum full-power frequency | $5000$ | $\mathrm{Hz}$ |
$f_{max}$ | -3dB low-pass cut-off frequency | $6000$ | $\mathrm{Hz}$ |
$f_{min}$ | -3dB high-pass cut-off frequency | $300$ | $\mathrm{Hz}$ |
$\tau_{i}$ | Integration time constant | $1.59 \cdot 10^{-5}$ | $\mathrm{s}$ |
achievements specification
Table achievements specification symbol | description | value | units |
$V_{onoise WLI p}$ | DIN A weighted RMS output noise with PMOS, W, L, and ID | $1.089 \cdot 10^{-5}$ | $\mathrm{V}$ |
$V_{onoise gmCissP}$ | DIN A weighted RMS output noise with g_m, and c_iss | $1.308 \cdot 10^{-5}$ | $\mathrm{V}$ |
budgets specification
Table budgets specification symbol | description | value | units |
$n_{Ri}$ | Max. contribution of R_i to the DIN A weighted squared output noise | $0.25$ | |
$n_{SRC}$ | Relative contribution of source to squared output noise | $0.02333$ | |