"Specifications"

Specifications

Initial specifications for this design step

The noise specifications at the beginning of this design step are listed below.

design specification

Table design specification
symboldescriptionvalueunits
$C_{i}$Required value of integrator capacitor$1.59 \cdot 10^{-9}$$\mathrm{F}$
$I_{fb}$Maximum peak-peak current through feedback network$4.022 \cdot 10^{-5}$$\mathrm{A}$
$L_{Mn}$Selected length input stage NMOS$1.0 \cdot 10^{-5}$$\mathrm{m}$
$R_{i}$Selected value of integrator resistor$1.0 \cdot 10^{4}$$\mathrm{\Omega}$
$Ri_{max}$Max. value of integrator resistor$1.0 \cdot 10^{4}$$\mathrm{\Omega}$
$SRCnoise$DIN A weighted RMS output noise, source + termination$1.819 \cdot 10^{-6}$$\mathrm{V}$
$c_{issN}$Selected input capacitance NMOS$2.839 \cdot 10^{-11}$$\mathrm{F}$
$c_{iss costs minN}$Required c_iss for minimum costs$2.839 \cdot 10^{-11}$$\mathrm{F}$
$c_{iss g m minN}$Required c_iss at g_m_min$1.194 \cdot 10^{-9}$$\mathrm{F}$
$g_{mN}$Selected transconductance input stage NMOS$3.086 \cdot 10^{-5}$$\mathrm{\mathtt{\text{S}}}$
$g_{m costs minN}$g_m for minimum costs$3.086 \cdot 10^{-5}$$\mathrm{\mathtt{\text{S}}}$
$g_{m minN}$Minimum transconductance input stage NMOS$1.56 \cdot 10^{-5}$$\mathrm{\mathtt{\text{S}}}$

performance specification

Table performance specification
symboldescriptionvalueunits
$L_{s}$Source inductance$0.12$$\mathrm{H}$
$R_{s}$Source resistance$875$$\mathrm{\Omega}$
$R_{t}$Termination resistance$7547.0$$\mathrm{H}$
$V_{onoise}$DIN A weighted output voltage noise$1.191 \cdot 10^{-5}$$\mathrm{V}$
$Vi_{ADC}$Peak-peak input voltage ADC$0.9$$\mathrm{V}$
$Vi_{pp}$Maximum peak-peak input voltage$0.3215$
$f_{fp}$Maximum full-power frequency$5000$$\mathrm{Hz}$
$f_{max}$-3dB low-pass cut-off frequency$6000$$\mathrm{Hz}$
$f_{min}$-3dB high-pass cut-off frequency$300$$\mathrm{Hz}$
$\tau_{i}$Integration time constant$1.59 \cdot 10^{-5}$$\mathrm{s}$

achievements specification

Table achievements specification
symboldescriptionvalueunits
$V_{onoise gmCissN}$DIN A weighted RMS output noise with g_m, and c_iss$1.308 \cdot 10^{-5}$$\mathrm{V}$

budgets specification

Table budgets specification
symboldescriptionvalueunits
$n_{Ri}$Max. contribution of R_i to the DIN A weighted squared output noise$0.25$
$n_{SRC}$Relative contribution of source to squared output noise$0.02333$

Updated specifications

After finishing this design step the updated specifications are:

design specification

Table design specification
symboldescriptionvalueunits
$C_{i}$Required value of integrator capacitor$1.59 \cdot 10^{-9}$$\mathrm{F}$
$IC_{Mn}$Inversion coefficient input stage NMOS$0.008771$
$ID_{Mn}$Operating current input stage NMOS$1.066 \cdot 10^{-6}$$\mathrm{A}$
$I_{fb}$Maximum peak-peak current through feedback network$4.022 \cdot 10^{-5}$$\mathrm{A}$
$L_{Mn}$Selected length input stage NMOS$1.0 \cdot 10^{-5}$$\mathrm{m}$
$M_{Mn}$Number of fingers input stage NMOS$27$
$R_{i}$Selected value of integrator resistor$1.0 \cdot 10^{4}$$\mathrm{\Omega}$
$Ri_{max}$Max. value of integrator resistor$1.0 \cdot 10^{4}$$\mathrm{\Omega}$
$SRCnoise$DIN A weighted RMS output noise, source + termination$1.819 \cdot 10^{-6}$$\mathrm{V}$
$W_{F Mn}$Finger width input stage NMOS$5.0 \cdot 10^{-5}$$\mathrm{m}$
$W_{Mn}$Selected width input stage NMOS$0.00135$$\mathrm{m}$
$c_{issN}$Selected input capacitance NMOS$2.839 \cdot 10^{-11}$$\mathrm{F}$
$c_{iss Mn}$Obtained input capacitance input stage NMOS$2.74 \cdot 10^{-11}$$\mathrm{F}$
$c_{iss costs minN}$Required c_iss for minimum costs$2.839 \cdot 10^{-11}$$\mathrm{F}$
$c_{iss g m minN}$Required c_iss at g_m_min$1.194 \cdot 10^{-9}$$\mathrm{F}$
$g_{mN}$Selected transconductance input stage NMOS$3.086 \cdot 10^{-5}$$\mathrm{\mathtt{\text{S}}}$
$g_{m Mn}$Obtained transconductance input stage NMOS$3.086 \cdot 10^{-5}$$\mathrm{\mathtt{\text{S}}}$
$g_{m costs minN}$g_m for minimum costs$3.086 \cdot 10^{-5}$$\mathrm{\mathtt{\text{S}}}$
$g_{m minN}$Minimum transconductance input stage NMOS$1.56 \cdot 10^{-5}$$\mathrm{\mathtt{\text{S}}}$

performance specification

Table performance specification
symboldescriptionvalueunits
$L_{s}$Source inductance$0.12$$\mathrm{H}$
$R_{s}$Source resistance$875$$\mathrm{\Omega}$
$R_{t}$Termination resistance$7547.0$$\mathrm{H}$
$V_{onoise}$DIN A weighted output voltage noise$1.191 \cdot 10^{-5}$$\mathrm{V}$
$Vi_{ADC}$Peak-peak input voltage ADC$0.9$$\mathrm{V}$
$Vi_{pp}$Maximum peak-peak input voltage$0.3215$
$f_{fp}$Maximum full-power frequency$5000$$\mathrm{Hz}$
$f_{max}$-3dB low-pass cut-off frequency$6000$$\mathrm{Hz}$
$f_{min}$-3dB high-pass cut-off frequency$300$$\mathrm{Hz}$
$\tau_{i}$Integration time constant$1.59 \cdot 10^{-5}$$\mathrm{s}$

achievements specification

Table achievements specification
symboldescriptionvalueunits
$V_{onoise WLI n}$DIN A weighted RMS output noise with NMOS, W, L, and ID$1.108 \cdot 10^{-5}$$\mathrm{V}$
$V_{onoise gmCissN}$DIN A weighted RMS output noise with g_m, and c_iss$1.308 \cdot 10^{-5}$$\mathrm{V}$

budgets specification

Table budgets specification
symboldescriptionvalueunits
$n_{Ri}$Max. contribution of R_i to the DIN A weighted squared output noise$0.25$
$n_{SRC}$Relative contribution of source to squared output noise$0.02333$

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SLiCAP: Symbolic Linear Circuit Analysis Program, Version 2.0.1 © 2009-2023 SLiCAP development team

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Last project update: 2023-12-28 22:44:08