==================== 20-11-2025: CS stage ==================== Lecture: EE4109-4 Location: Hall Ampere (36.HB.01.670) Time: 08:45 - 10:30 .. image:: ../../../img/colorCode.svg :alt: color coded resistors SPICE test circuits =================== We will present two `spice test circuits `_ for the determination of properties of the intrinsic CS stage and the CS stage driven from and terminated with an parallel RC network. - output voltage and current drive capability - input voltage and current drive requirement - input impedance and output impedance - forward and reverse transfer parameters - pole splitting The biased CS stage =================== .. include:: ../../../topics/CSstage/CSstage-intro.rst .. include:: ../../../topics/CSstage/CSstage-intrinsic.rst .. include:: ../../../topics/CSstage/CSstage-source-load.rst Group exercise ============== - Compare the Bode plots of the small-signal transimpedance factor of the biased CS stage operating in the active forward region, plotted with ngspice using the BSIM model, and with SLiCAP using the EKV model. Use minimum geometry, VDS = 0.9V, and weak, moderate and strong inversion. - Study the influence of geometry and inversion (discuss with each other, and verify)