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ADC residue amplifier
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.. image:: ../img/colorCode.svg
    :alt: color coded resistors

A residue amplifier in a 12-bit pipeline ADC with a 2-bit first stage must provide an ideal gain of 4 to resolve the remaining 10 bits of the signal. Operating at a sampling frequency of 20 MS/s with a 50% duty cycle, the amplifier is constrained to a 25 ns settling window. The amplifier should be driven by a differential voltage where the load of the amplifier is equal to the input impedance of the amplifier since the same amplifier is used in the next stage of the pipeline ADC.  
The residue amplifier must achieve a settling accuracy of -66 dB and a signal-to-noise ratio (SNR) of at least 66 dB in the time window.

#. The residue amplifier must operate from 0 to 70 degrees Celsius.
#. The circuit must operate from a 1.8 V ±5% power supply. 
#. The total power dissipation, excluding the biasing circuit, must be below 0.3 mW. 
#. The circuit must be realized in a CMOS18 process.