Circuit data

Circuit data#

Circuit diagram#

img/CSstageSLiCAP.svg

Netlist#

 1"CS stage"
 2* Z:\mnt\DATA\www\analog-electronics.eu\topics\CSstage\SLiCAP\cir\CSstage.asc
 3R1 out 0 {R_L}
 4XU1 out N001 0 0 CMOS18N W={W} L={L} ID={ID}
 5I1 0 N001 I value=0 dc=0 dcvar=0 noise=0
 6R2 N001 0 {R_s}
 7.param W=40u L=500n ID=100u R_L=10k R_s=10M
 8.lib SLiCAP.lib
 9.backanno
10.end
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