Introduction to Class D amplifiers¶
The goal of this presentation is for the participants to achieve a sufficient level of understanding of class D amplifiers, such that they are able to design application specific amplifiers and/or evaluate the application of existing amplifier solutions.
The goal of applying switched amplifiers or class D amplifiers, is to achieve a high power efficiency.
Basic operation¶
In class D amplifiers, a power output stage commutes its output at a high frequency (above Nyquist rate) between the positive and the negative supply terminal. In order to suppress undesired high-frequency components at the load, a low-pass filter can be placed between the switching output stage and the load. The duty cycle of the switching signal sets the low-frequency value of the load voltage, which contains the information for the load.
The figure above shows the structure of a class D amplifier.
Amplifier types¶
At the start of the design, the function and topology of the class D amplifier needs to be defined. Questions that need to be answered at this stage are:
Which physical quantity represents the driving information for the amplifier
Current (current output DAC)
Voltage (voltage output DAC)
Which physical quantity represents the information that needs to be transferred to the load
Current (Controlling the intensity of a LED, the torque of a motor, etc.)
Voltage (Controlling the sound pressure delivered by a loudspeaker, the speed of a motor, etc.)
Power (Controlling the heat that is generated by a heating element)
In which way are the source and the load electrically coupled to the system
They are electrically isolated with respect to each other
They both share the system ground
Amplifier operating principles¶
We will evaluate the relation between the output voltage of a class D output stage and the duty cycle of its switching signal. From this we will calculate the ripple current in the inductor and study two switching strategies.
Let \(\tau\) be the on time interval over which the switch \(S\) connects to \(V_{P}\), and \(T-\tau\) the time interval in which it connects to \(-V_{N}\). The average (DC) voltage \(V_{o}\), at the output of the filter then can be obtained as:
If the peak to peak ripple voltage \(V_{R}\) at the output of the filter is much smaller than the peak to peak signal voltage \(V_{P}+V_{N}\) at its input, the peak to peak ripple current through the inductor \(L\) can be found from:
In which \(i_{L}(t)\) is the inductor current. After substitution of
in which \(I_{R}\) is the peak to peak value of the ripple current, we obtain:
Fixed frequency or fixed ripple current¶
Basically two different switching strategies can be distinguished:
Fixed frequency switching
With fixed frequency switching, the output stage switching frequency is coupled to an external clock. Fixed frequency switching has the advantage that the frequency spectrum of interference signals generated by the output stage has components at integer multiples of the switching frequency only. This makes it easy to define operating frequencies for system parts that are sensitive to these interference signals. At a switching frequency \(f\), the ripple current varies with the output voltage according to:
\[I_{R}=\frac{\left( V_{N}+V_{o}\right) \left( V_{P}-V_{o}\right) }{fL\left( V_{P}+V_{N}\right) }\]With \(V_{N}=V_{P}\) \(=V_{S}\), this simplifies to
\[I_{R}=\frac{V_{S}^{2}-V_{o}^{2}}{2fLV_{S}}\]Hence, the peak to peak value of the ripple current reaches its maximum at zero output voltage, which means at no load for a half-bridge driver with resistive load and symmetrical supply. With increasing load voltage excursion the ripple current decreases. This may be beneficial to the losses in the inductor.
Fixed ripple current switching
The switching instants of many self-oscillating class-D amplifiers are set by the threshold levels for the ripple current. When the ripple current reaches its positive maximum, the output switches to its low state and when the ripple current reaches its negative maximum the output switches to its high state. With a fixed peak to peak value of the ripple current, the operating frequency \(f=1/T\) can be found as:
\[f=\frac{\left( V_{N}+V_{o}\right) \left( V_{P}-V_{o}\right) } {I_{R}L\left( V_{N}+V_{P}\right) }\]With \(V_{N}=V_{P}\) \(=V_{S}\), this simplifies to :
\[f=\frac{V_{S}^{2}-V_{o}^{2}}{2I_{R}LV_{S}}\]Hence, fixed ripple current switching has the advantage that the switching frequency decreases with the output voltage excursion. This results in a reduction of switching losses for large signal excursions. As a result, the efficiency of fixed ripple current switching amplifiers may be better than that of comparable fixed frequency switching amplifiers. The frequency spectrum of interference signals is not periodic. In fact, a self oscillating class D amplifier can be viewed upon as a noise shaping circuit.
Power MOS switching¶
Before discussing the switching behavior of a power MOS half bridge class D output stage, we will resume the relevant (and simplified) device equations for a MOS transistor. Device parameters for static operation are:
\(\beta:\) the transconductance factor \(\mathrm{[\frac{A^2}{V}]}\)
\(V_{T}:\) the threshold voltage [V]. N-channel power MOS transistors are usually normally-off types (\(V_{T}>0\)).
The device equations for the forward biased region (\(V_{GS}>0\) and \(V_{DS}>0\) for a normally-off N-channel MOS) are given below. Forward bias operation itself is divided in three regions.
Cut-off region: \(V_{GS}<V_{T}\)
\[I_{DS}=0\]Saturation region: \(V_{DG}>-V_{T}\) or \(V_{DS}>V_{GS}-V_{T}\)
\[I_{DS}=\beta\left( V_{GS}-V_{T}\right) ^{2}%\]Linear region: \(V_{DG}\leq-V_{T}\) or \(V_{DS}\leq V_{GS}-V_{T}\)
\[\begin{split}\begin{aligned} I_{DS} & =\beta V_{DS}\left( 2\left( V_{GS}-V_{T}\right) -V_{DS}\right)\\ \left. R_{DS}\right\vert _{V_{DS}=0} & =\frac{1}{2\beta\left( V_{GS}-V_{T}\right) } \end{aligned}\end{split}\]
The dynamic behavior of the MOS can be described by adding the capacitances \(C_{gs}\), \(C_{gd}\) and \(C_{ds}\). The capacitance \(C_{gd}\) is sometimes referred to as the reverse transfer capacitance or the feedback capacitance. The total input capacitance with shorted output is \(C_{iss}=C_{gs}+C_{gd}\). The total output capacitance with shorted input is \(C_{oss}=C_{ds}+C_{gd}\).
The capacitances \(C_{gd}\) and \(C_{ds}\) are voltage dependent: \(C_{gd}\) depends on the effective channel length, which in turn depends on the drain-gate voltage, while \(C_{ds}\) is the depletion capacitance of the body diode, which depends on \(V_{ds}\). Because of this nonlinear behavior, charge models are often used instead. Important charge parameters are \(Q_{G}\): the total gate charge, which is divided over on \(C_{gs}\) and \(C_{gd}\), and \(Q_{O}\) the total output charge, which is divided over \(C_{gd}\) and \(C_{ds}\).
If the body diode is conducting, charge is built up in it because of the non-zero life-time of charge carriers. The amount of charge is proportional to the forward diode current. This charge is referred to as the “reverse recovery charge” \(Q_{RR}\). The diode stops conducting after all this charge has been removed.
The static diode characteristic describes the diode current \(I_{D}\) as a function of its voltage \(V_{D}\) (both positive for forward bias):
In which \(I_{s}\) is a device parameter that depends on the fabrication process and on the temperature, \(k\) is Boltzmann’s constant: \(1.38\times10^{-23}\) [J/K], \(q\) is the electron charge \(1.6\times10^{-19}\) [C], and \(T\) the absolute temperature [K].
Switching behavior¶
The figure below shows a half-bridge output stage for bipolar operation. With the aid of this figure, we will discuss its switching behavior. We will assume equal MOS transistors and equal drivers for the upper and the lower stage. The gate drivers a capable of driving the gate with a current \(\pm I_{G}\), up to a maximum voltage \(V_{G}\) and a minimum of \(0\) [V] and the internal delay of the gate drivers is assumed zero.
We also asume the DC load current \(I_{load}\) larger than the peak to pek ripple current \(I_{R}\).
The figure below illustrates the switching behavior for \(I_{load}>0\) (source operation). We will start our observations in the state that the upper MOS conducts and the lower MOS is switched off, at the end of the “high-state” of the output stage.
At some time instant, the input of the upper MOS gate-driver goes low. It takes some time \(\tau_{d1}\) before the current in the lower FET drops below \(I_{load}\). During this time the input capacitance \(C_{iss}\) of the MOS is discharged by \(I_{G}\) and the gate voltage drops from \(V_{G}\) to \(V_{T}% +\sqrt{\frac{I_{load}}{\beta}}\). Nothing happens at the output of the switch. The delay time \(\tau_{dpL}\) can thus be evaluated as:
\[\tau_{d1}=\frac{C_{iss}\left( V_{G}-V_{T}-\sqrt{\frac{I_{load}}{\beta}% }\right) }{I_{G}}%\]After this delay, the upper MOS goes to its off-state. The rate of change of the voltage at the output of the switch can now be determined by two different mechanisms, the slowest of the transitions occurs:
Low-current switching: the rate of change of the output voltage is set by the load current discharging the output capacitance of the lower MOS and discharging the output capacitance of the upper MOS. In this case we find:
\[\tau_{f}=\frac{2\left( V_{P}+V_{N}\right) C_{oss}}{I_{load}} \label{eq-slowTr}%\]High current switching: the rate of change of the output voltage is set by the maximum sink current of the gate driver discharging \(C_{gd}\) of the upper MOS. In this case we find:
\[\tau_{f}=\frac{2\left( V_{P}+V_{N}\right) C_{gd}}{I_{G}}\]The dead time \(\tau_{d}\) is smaller than the largest of the two above values for \(\tau_{r}\). This occurs at low current switching with a small dead time. The lower MOS then starts conducting before the switch output voltage reaches \(V_{N}.\) If the drive conditions for both MOS transistors are equal (as assumed), during the dead time the transition behavior is governed by the first of the above mechanisms, while after the dead time, it is governed by the second mechanism.
Voltage and current waveforms for a sourcing half-bridge driver: Upper: gate drive signalsMiddle: switch output voltage Lower: MOS currents, supply currents, ripple current and average load current.
The behavior during the “low state” of the half bridge also differs for various drive-load conditions.
Low current switching with a large dead time \(\tau_{d}\).
For this situation we assume \(\tau_{d}>\tau_{dpL}+\tau_{r}\). In this case the body diode of the lower MOS conducts during the remaining part of \(\tau_{d}\) and the output voltage of the switch becomes \(V_{N}-V_{F}\), in which
\[V_{F}=\frac{kT}{q}\ln\frac{I_{load}}{I_{s}}\]Resonant switching occurs if the lower MOS switches to its on state at the same instant that the switch output voltage reaches \(V_{N}\). Resonant switching is beneficial for low EMI, but in class D amplifiers it occurs only during specific drive and load conditions for the output stage.
At the end of the dead time the input signal for the lower gate driver switches to high. Nothing happens until the gate of the lower MOS is charged to \(V_{T}\). Hence, we find:
\[\tau_{d2}=\frac{C_{iss}V_{T}}{I_{G}}\]After the gate of the lower MOS has been charged to \(V_{T}\), it starts conducting and the output voltage becomes \(V_{N}\).
After some time the input signal for the lower MOS driver becomes zero. After a delay \(\tau_{d3}=\tau_{d1}\), the body diode takes over the conduction from the upper MOS.
At he end of the dead zone the driver of the upper MOS driver is activated and after a delay the upper MOS starts conducting. This first discharges the diode. The total delay time until the output voltage starts rising equals:
\[\tau_{d3}=\frac{C_{iss}V_{T}}{I_{G}}+\tau_{RR}\]In which \(\tau_{RR}\) is the reverse recovery time of the body diode. This time strongly depends on the rate of change of the current during reverse recovery, which in turn strongly depends on the voltage drive capabilities of the gate driver and the total parasitic inductance in the discharge path. Peak currents during reverse recovery can be very large and contribute significantly to EMI.
After the reverse recovery the output voltage risess, as fast as the gate-drain capacitance can be charged, from \(-V_{N}\) to \(V_{P}\). Hence, we have
\[\tau_{f}=\frac{C_{gd}\left( V_{P}+V_{N}\right) }{I_{G}}\]Then the output stage is again in its “high state”.
Shoot-through¶
One speaks of “shoot-through” if the gate-source voltage of both the upper and lower MOS exceed the threshold voltage \(V_{T}\). This results in large power supply currents and excessive dissipation in the MOS transistors. Shoot-through occurs if the rage of change of the output voltage of the switch causes a voltage drop across the total gate series resistance \(R_{G}\), larger than \(V_{T}.\) In this case, where we assume equal components for the upper and the lower halves, shoot-through prevention requires:
Estimation of output stage losses¶
The losses in the output stage are usually estimated for the worst case situation:
At maximum switching frequency
At maximum load current
The losses are built up from the following components:
MOS conduction losses \(P_{cM};\) these are the losses in \(R_{dsOn}\):
\[P_{cM}\approx I_{load}^{2}R_{dsOn}\frac{T-2\tau_{d}}{T}\]If a body diode becomes forward biased during the dead time \(\tau_{d}\), we have body diode conduction losses \(P_{cD}\):
\[P_{cD}\approx I_{load}V_{F}\frac{2\tau_{d}}{T}\]Output charge losses \(P_{oQ}\) (for two transistors):
\[\begin{split}\begin{aligned} P_{oQ} & \approx2fQ_{o}\left( V_{P}+V_{N}\right) \\ & \text{or}\nonumber\\ P_{oQ} & \approx2fC_{oss}\left( V_{P}+V_{N}\right) ^{2} \end{aligned}\end{split}\]If the body diode was forward biased during the dead time \(\tau_{d}\), we have reverse recovery losses \(P_{RR}\):
\[P_{RR}=Q_{RR}\left( V_{P}+V_{N}\right)\]Switching losses \(P_{sw}\) occur due to a non-zero overlap of the drain-source voltage and the non-capacitive part of the drain current during switching.
\[\begin{split}\begin{aligned} P_{sw} & =\frac{2}{T}\int_{0}^{\tau_{sw}}\left( V_{P}+V_{N}\right) \left( 1-\frac{t}{\tau_{sw}}\right) I_{load}\frac{t}{\tau_{sw}}dt\\ & =\frac{\tau_{sw}I_{load}\left( V_{N}+V_{P}\right) }{3T} \end{aligned}\end{split}\]The switching time \(\tau_{sw}\) is the time that elapses during the charging or discharging of \(C_{gd}\):
\[\tau_{sw}=\frac{C_{gd}\left( V_{P}+V_{N}\right) }{I_{G}}\]
Gate driver losses¶
The gate griver losses \(P_{G}\) for one gate driver circuit equal:
Or, alternatively:
Losses versus EMI¶
If the switching losses \(P_{sw}\) dominate over the charge losses and conduction losses, they can be reduced by increasing the gate drive current. This, however, is at the expense of the EMI because of the faster transients.
If the switching losses \(P_{sw}\) are not dominant, they can be increased thereby reducing the EMI. This can be achieved by inserting a resistor in series with the gate of the MOS. Care should be taken that no shoot-through occurs.