Setting up the initial biasing scheme

Setting up the initial biasing scheme#

In this section, we will discuss the design of an initial biasing scheme of an amplifier. The associated design steps are:

Set up the signal path design with four bias sources per transistor, as discussed in Chapter Amplification Mechanism.
Add the power supply voltage sources to the signal path diagram.
Redirect the current sources via the supplies and the ground and minimize the number of bias sources.
If necessary, add bias currents through voltage sources in such a way that those voltage sources can be replaced with passive nonlinear resistors with a voltage source character.
If necessary, add (or change) supply voltages in such a way that the bias current sources can be replaced with passive nonlinear resistors with a current source character.

We will demonstrate this for a single-transistor CE and CS stage amplifier in section CE and CS stage biasing, for local feedback stages in section Biasing of local-feedback stages, for cascode stages in section Biasing of cascode stages for anti-series stages in section Biasing of anti-series stages, for complementary parallel stages in section Biasing of complementary-parallel stages.

CE and CS stage biasing#

In this section, we will demonstrate the biasing of a transimpedance amplifier with a single CE or CS stage.

../_images/CE-CSstageBasicBias.svg — Fig. 491 Starting points for the biasing of a transimpedance amplifier with a CE stage or CS stage. Please note that $I_{s}$ and $V_{ℓ}$ represent the source signal and the load signal, respectively. Their values are zero in the quiescent operating point. A. Biased CE stage with zero quiescent current through V1 and V1 and nonzero quiescent voltages across the current sources. B. Biased CS stage with zero quiescent voltage across I2 and I3 and nonzero quiescent currents through V1 and V2.#

Fig. 491A shows the signal diagram of the transimpedance amplifier equipped with a single CE stage and its four bias sources. In this arrangement, the bias voltage sources carry no current, while the voltages across these sources equal the operating point voltages. Fig. 491B shows the signal diagram of the transimpedance amplifier equipped with a single CS stage with the four bias sources. In this arrangement, the bias voltage sources carry the quiescent operating currents, while the voltage across the bias current sources equals zero. Both arrangements of bias sources can be converted into each other through application of the Blakesley\cite[2cm]{Blakesley1994} voltage shift theorem.

Fig. 492 shows the initial biasing schemes of both circuits from Fig. 491. Please note that the voltage sources V1 and V2 in both circuits cannot be replaced with passive nonlinear resistors. In Fig. 491A the current through these sources is zero, while the voltage across them is nonzero. Hence, their $V - I$ characteristic cannot pass through the origin. In Fig. 491B the product of the branch voltage and the branch current is negative. Hence, by definition, these are active elements.

../_images/CE-CSstageBasicBiased.svg — Fig. 492 Initial biasing schemes of the transimpedance amplifiers from Fig. 491: A. Initial biasing scheme of the CE stage transimpedance amplifier. B. Initial biasing scheme of the CS stage transimpedance amplifier.#

In order to replace these voltage sources with passive elements, we need to add current through them in such a way that the power dissipation in the element is positive. If we do this for V2, we need a passive element with a current source character (I5), as shown in Fig. 493. Since this element itself needs to be passive, it requires a nonzero voltage across it. This voltage needs to be provided by the negative power supply source V4.

The biasing of the transimpedance amplifier with the CS stage from Fig. 492B proceeds in a similar way. In order to replace the bias voltage sources with passive devices, the current direction in these sources needs to be changed. This can be accomplished by changing the initial biasing arrangement from Fig. 491B, to the one used in Fig. 491A.

../_images/CEstageBasicBiasedDual.svg — Fig. 493 Initial biasing schemes of the transimpedance amplifiers from Fig. 491 A. All bias sources have now been derived from the power supply voltages with the aid of passive nonlinear resistive elements.#

The result for the CMOS version of the transimpedance amplifier is then similar to that of the bipolar version; it is shown in Fig. 494. Please note that the bulk of the NMOS has now been connected to the most negative voltage in the circuit. Whether this is necessary or not, depends on the applied integrated circuit technology.

../_images/CSstageBasicBiasedDual.svg — Fig. 494 Initial biasing schemes of the transimpedance amplifiers from Fig. 491 B. All bias sources have now been derived from the power supply voltages with the aid of passive nonlinear resistive elements.#

At a later stage of the biasing, we will discuss means to reduce the number of floating voltage sources. Now, we will continue with designing initial biasing schemes for other kinds of stages.

Biasing of local-feedback stages#

The biasing of local-feedback stages is performed similarly as the biasing of CE or CS stages. The starting point is the biased N or P device with its four bias sources. The feedback networks are added around the biased devices. In this section, we will discuss the design of an initial biasing scheme for local feedback stages with n-type devices. The biasing of stages with p-type devices proceeds in a similar way, but the biasing elements have opposite signs. We will use examples with BJT or MOS devices. The biasing procedure is independent of the device type and technology. The implementation of the biasing scheme, however, strongly depends on the technology and the device type.

Setting up the initial biasing scheme of CD and CC stages#

Fig. 495 shows an NPN CC stage with its source, load and bias sources. A similar circuit can be designed with a MOS transistor.

Similar as with the biasing of the CE and CS stage, the bias quantities have to be derived from the power supply voltages with the aid of the nonlinear resistive elements. This process is illustrated in Fig. 496.

Fig. 496A shows the result after adding the power supply voltage $V_{P}$ , redirecting the current sources via the power supply and ground, and replacing them with nonlinear resistors. In order to have a nonzero voltage drop across I2, a negative supply voltage $V_{N}$ has to be added. After doing so, I2 can be replaced with a nonlinear resistor with a current source character. Fig. 496B shows the addition of a current $I_{V_{1}}$ through V1, so that this voltage source can be replaced with a nonlinear resistor.

../_images/biasingCCstage.svg — Fig. 496 Biasing of the CC stage. Please note that $V_{s}$ and $V_{ℓ}$ represent the signal voltages. These voltages are zero in the quiescent operating point. A. Addition of the power supply voltage to the signal path from Fig. 495, redirecting of the current sources via the power supplies and the ground and replacing them with passive nonlinear resistors. B. Replacing {\tt{V1}} with a passive nonlinear resistor, requires the addition of a bias current $I_{V_{1}}$ through it.#

The biasing of an NMOS and a PMOS CD stage proceeds in a similar way; it is left as an exercise to the reader.

Setting up the initial biasing scheme of CG and CB stages#

Fig. 497 shows an NMOS CG stage with its source, load and bias sources. A similar circuit can be designed with bipolar transistor. The biasing of an NPN and PNP CB stage is left as an exercise to the reader.

Similar as with the biasing of the CE and CS stage, the bias quantities have to be derived from the power supply voltages with the aid of the nonlinear resistive elements. This process is illustrated in Fig. 498.

Fig. 498A shows the result after adding the power supply voltages, redirecting the current sources via the power supply voltage sources and replacing them with nonlinear resistors. In order to have a nonzero voltage drop across I2, a negative supply voltage $V_{N}$ has been added. Fig. 496B shows the addition of a current $I_{V_{1}}$ through V1, so that this voltage source can be replaced with a nonlinear resistor. The biasing of an NMOS CD stage proceeds similarly. This is left as an exercise to the reader.

Initial biasing of other three-terminal configurations#

Until now, we have discussed the design of initial biasing schemes for some basic amplifier stages of which the source and the load share one terminal. By taking the initial bias scheme from Chapter Amplification Mechanism as starting point, both the source and the load operate at $(V, I) = (0, 0)$ . Hence, the DC voltage across the source and the load and the DC current through the source and the load all equal zero. These conditions are not always required nor desired. In fact, some signal sources like PIN diodes in optical receivers require a nonzero DC bias voltage for high-speed operation, while a low-noise amplifiers for radio applications may need to drive a mixer that requires a nonzero DC bias current. A signal source or a load that needs, or is allowed to operate under nonzero bias conditions can be modeled with the aid of a bias-free source or load and bias sources, similar to the bias sources to two-terminal elements in Chapter Amplification Mechanism. A biasing example with added output offset can be found in Chapter Introduction to amplifier biasing.

../_images/biasingCGstage.svg — Fig. 498 Biasing of the CG stage. Please note that $I_{s}$ and $I_{ℓ}$ represent the signal currents. These currents are zero in the quiescent operating point. A. Addition of the power supply voltage to the signal path from Fig. 497, redirecting the current sources via the power supplies and the ground and replacingthem with passive nonlinear resistors. B. Replacing the bias voltage sources from Fig. 498 A with passive nonlinear resistors requires the addition of bias currents through them.#

Although the return path for the source signal and the load signal, in three terminal amplifiers, are the same, they do not always need to operate at the same DC voltage with respect to the ground. If the source and the load share the signal return paths, but allow a DC offset between their common terminal, a DC bias voltage can be added to the biasing scheme. At a later stage of the design, the number of voltage sources can minimized.

Example

In this example we will discuss the design of a series stage with an NPN transistor, of which the load:

is a nonlinear resistor,
is electrically isolated from the source and the ground,
is allowed to operate at a nonzero common-mode voltage,
must be biased with a current $I_{Q},$
carries a voltage $V_{Q}$ at this bias current.

Fig. 499 shows a model of this load.

The series stage will be driven from a voltage source with a source impedance $Z_{s},$ of which one terminal is connected to the ground. The source should operate at zero bias current and zero bias voltage. The series stage should provide a voltage-to-current transfer for signals of which the frequency components of interest include zero (DC).

Fig. 500 shows the circuit diagram of the biased series stage connected to its source and load.

Fig. 501 shows the biasing scheme after the power supply sources have been added, the bias current sources have been redirected via the power supplies and replaced with passive nonlinear resistors with a current source character. The negative power supply voltage source V3 is required for biasing I3. The bias voltage across I4 amounts $V_{C E}$ . It can be increased by connecting I4 to the negative supply as well.

The bias current through V1 equals zero. In order to replace this voltage source with a passive nonlinear resistor, a bias current needs to be added. The biasing scheme can be simplified by taking the operating current of the BJT equal to that of the load: $I_{C} = I_{Q}$ . Changing the operating current or voltage of an amplifier stage, a biasing element, the source, or the load is one of the techniques to simplify the biasing scheme of an amplifier. We will give more examples of the application of this technique at a later stage. The result of the above actions is shown in Fig. 502.

../_images/BJTseriesStageStartBias.svg — Fig. 500 Biased series stage, driven from its source and loaded with the biased load from Fig. 499.#

../_images/BJTseriesStageStartBiasSimplified.svg — Fig. 501 Simplified biasing scheme for the circuit from Fig. 500.#

../_images/BJTseriesStageStartBiasSimplified-2.svg — Fig. 502 Biasing scheme for the circuit from Fig. 501 for the case in which $I_{Q} = I_{C}$ .#

Although we confine ourselves in this chapter to the design of the initial biasing scheme of amplifiers, it may be helpful to show a possible final implementation of the biasing of the series stage from the preceding example. By doing so, it will become clear that separation of the design of the signal path and the biasing helps us with clearly defining requirements and design limits for biasing circuitry before designing them. This makes it possible to estimate the feasibility of the biasing of an amplifier (stage) at an early stage of the design.

In the following we will show relatively simple implementation of the biasing in which the biasing elements with a current source character will be replaced with resistors and the biasing element with a voltage source character will be replaced with a diode.

Example

Fig. 503 shows a simple implementation of the biasing scheme from Fig. 502. In this implementation the nonlinear resistors with a current source character have been replaced with linear resistors and the nonlinear resistor with a voltage source character (V1) has been replaced with a diode. By doing so, the signal performance of the series stage from Fig. 502 differs from that of the initial series stage from Fig. 500:

The input impedance of the series stage is decreased, this reduces the transadmittance of the stage.
The spectral densities of the equivalent input noise sources of the stages are increased.
The nonzero conductance of R3 increases the transadmittance of the stage.

Another disadvantages of this implementation is that the PSSR for both positive and negative supply voltages is not as good as it would be using nonlinear resistors with a current source character.

Although the biasing solution in presented in the preceding example seems attractive because of its low complexity, the penalties on the signal behavior may be too large. Hence, the design of the biasing elements should start with setting up their performance specification. This will be discussed at a later stage.

Biasing of cascode stages#

In Chapter Multi-stage Feedback Amplifiers, we have introduced the cascode stage as a basic amplifier stage that consists of two transistors. The reason for this is that, when applied in negative feedback amplifiers, the CG or CB stage does not add a dominant pole to the loop gain poles product. In this section we will study the biasing of this cascode stage.

../_images/biasedNmosCascode.svg — Fig. 504 Initial schematic of a biased NMOS cascode stage.#

Fig. 504 shows an NMOS cascode stage with its initial bias sources. Each of the two transistors of the cascode stage is biased with the aid of four bias sources. The voltages and currents provided by these sources should be derived from the power supply voltage. Fig. 505 shows two steps of this biasing process.

Fig. 505A shows that the biasing scheme can be simplified by raising the voltage level of Q2 with respect to the ground. This is done by shifting the voltage source V2 through the device. It then appears in series with V3 and V4. The bias current sources have been redirected via the power supply and replaced with nonlinear resistors with a current source character.

../_images/biasingNmosCascode.svg — Fig. 505 Biasing of the NMOS cascode stage: A. Current sources replaced with biased passive elements B. Voltage sources replaced with biased passive elements#

Fig. 505B shows the result after bias currents have been added through the bias voltage sources. By doing so, these bias sources can be replaced with passive nonlinear resistors. The negative supply source V5 is added to obtain a positive voltage drop across the current source elements I4 and I5. As a matter of fact, the positive supply voltage $V_{P}$ , or the drain-to-source voltages of the transistors may need to be adjusted to obtain sufficiently large bias voltages for I1, I2 and I3.

Changing the voltage level and the bias voltages of devices are techniques that can be used for simplification of the biasing scheme. These techniques will be discussed at a later stage.

Another technique that can be applied for simplification of the biasing scheme is the use of complementary transistors. Fig. 506 shows the so-called folded cascode stage in which the CG stage transistor is the complementary type of the CS stage transistor. All the previously mentioned techniques have been used to simplify the biasing scheme that now requires current source elements only. The application of complementary devices will also be discussed at a later stage.

Biasing of anti-series stages#

In this section, we will discuss the biasing of the balanced anti-series stages. In Chapter Balancing techniques, we have seen that anti-series stages can be biased with common-mode current sources only (see Fig. 199). Fig. 507 shows the way in which this is done for an NMOS anti-series stage. The bias current sources have been replaced with using nonlinear resistors with a current source character. However, by doing so, the node voltages with respect to ground are undefined. In fact, in this biasing concept, the differential pair is floating with respect to the ground.

In practice, we need to fix the common-mode voltages of the input port and the output port with respect to ground in such a way, that under all operating conditions, the biasing elements and the transistors are properly biased. This can be accomplished in various ways. In Chapter Introduction to amplifier biasing, several methods for common-mode biasing have been introduced. In order to grasp the idea that these are the concepts behind the circuit implementations given below, the reader is invited to study this chapter.

Source or load common-mode biasing#

Source or load common-mode biasing is a technique in which the common-mode voltage at the input port is defined by that of the source and/or the common-mode voltage at the output port is defined by that of the load. Fig. 508 shows an application of this technique for the case in which both the source and the load have a common-mode connection, and the common-mode voltages are fixed with the aid of nonlinear resistive elements.

../_images/diffPairNMOSbiasCM.svg — Fig. 508 Differential-pair NMOS stage of which the common-mode voltages at the input port and the output port have been fixed by those of the source and the load, respectively.#

This way of biasing requires a signal source or load that has a finite DC resistance to a common-mode voltage. Such source and load configurations are not always available. In those cases the common-mode voltages have to be defined by using different biasing techniques.

Brute force common-mode biasing#

Brute force common-mode biasing is a technique in which the common-mode level at a port is defined by connecting the terminals of the port with resistors to a common-mode reference voltage. Fig. 509 shows the application of this technique for fixing the common-mode voltage and the common-mode resistance of a signal voltage source that is floating with respect to the ground. The common-mode resistance of the source is reduced from infinity to $R_{c m}$ . This way of biasing may deteriorate the signal performance of the stage:

The bias resistors generate noise and increase the noise contribution of the equivalent input noise sources of the differential pair
The bias resistors attenuate the source signal and increase the influence of the source impedance on the signal transfer of the differential pair.

Local common-mode feedback#

Similar to the design of feedback amplifiers (see Chapter Design of feedback amplifier configurations), the common-mode impedances, voltages or currents can be fixed to an accurate value with the aid of negative feedback. Fig. 510 shows the concept for fixing the common-mode impedance and bias voltage of a floating port.

The open-circuit common-mode voltage of this circuit equals $V_{c m}$ and the common-mode impedance equals $\frac{1}{g_{c m}}$ . The differential-mode impedance is not affected by the common-mode feedback.

Fig. 511 gives an implementation of this principle with four equal NMOS transistors. In the quiescent operating point the gate-source voltages of these devices all equal $V_{G S}$ , which is the common-mode voltage of the port. As a result of the finite output resistance of the MOSFETs, the differential input resistance of the port is limited to $r_{d s},$ which is the DC output resistance of one transistor in its operating point. For a large differential input voltage range and a large differential-mode input resistance, the devices should be as long as possible and operate in strong inversion. In the following example we will plot the DC characteristics of the common-mode biasing circuit from Fig. 511.

Example

In this example we will evaluate the DC port characteristics of the circuit from Fig. 511. Fig. 512 shows the test circuit and the DC characteristics.

../_images/RcmVcmNMOS.svg — Fig. 512 Left: {SPICE} circuit for determination of the DC characteristics from Fig. 511. Right: Node voltages, common-mode and differential mode voltage as a function of the differential-mode input current.#

The listing of the SPICE input file is shown below:

RcmVcmNMOS
* File: RcmVcmNMOS.cir
* LTspice circuit file
.include CMOS18TT.lib
M1 1 1 0 0 C18nmos W=220n L=1u
M2 1 2 0 0 C18nmos W=220n L=1u
M3 2 2 0 0 C18nmos W=220n L=1u
M4 2 1 0 0 C18nmos W=220n L=1u
I1 0 1 10u
I2 0 2 10u
I3 1 2 0
.dc I3 -1u 1u 1n
.end

Over a differential input voltage range of $\pm 0.25$ V the differential input resistance is about $10$ M $Ω$ . Outside this range the input resistance drops and the differential-mode to common-mode conversion becomes significant.

../_images/diffPairNMOSfixInOutCmV.svg — Fig. 513 Anti-series CS stage of which the common-mode input voltage, the common-mode input resistance, the common-mode output voltage and the common-mode output resistance are fixed according to the method from Fig. 510.#

Fig. 513 shows an arrangement in which this type of biasing has been applied at both the input port and the output port of an anti-series CS stage. At the output port, the common-mode voltage is referred to the power supply voltage. It is controlled by four PMOS devices.

It should be noted that this way of common-mode biasing may result in a deterioration of the signal-to-noise ratio. Since the channel noise of the four MOS devices is uncorrelated, it contributes to differential current noise. This noise contribution can be kept low by making the bias currents of these devices as low as possible. In fact, this bias current should be large enough to maintain proper biasing for all values of the common-mode input current.

Another disadvantage of the circuit is its contribution to the differential-mode input capacitance of the biased port.

Feed forward common-mode biasing#

Feed forward common-mode biasing is a technique in which the common-mode voltage or current at the output port is fixed by means of fixing the common-mode voltage or current at the input port, together with the common-mode transfer of a balanced stage. This technique can be used to establish a well-defined common-mode output voltage in anti-series connected stages with DC parallel feedback at the output port:

The balanced common drain stage or the balanced common collector stage
The balanced shunt stage
Anti-series connected multiple-loop passive feedback stages with parallel feedback at the output port.

Fig. 514A shows the signal diagram of the balanced voltage follower, of which the common terminals of the stages (collectors or drains) have been connected to the ground. Please note that this does not affect the balanced operation if both the source and the load are truly balanced with respect to the ground. Since this stage has a common-mode voltage gain of unity, the common-mode voltage at the output port will be defined by that at the input port.

Fig. 514B shows the signal diagram of a balanced shunt stage with resistive feedback. In this circuit, the common terminal of the stages (the emitters of sources) have been left floating with respect to the ground. In this case, the common-mode voltage gain of the stage equals unity and the common-mode voltage at the output port can be defined by that at the input port. If the common terminal of the two stages is grounded the common-mode transresistance equals the DC feedback resistance. In that case, the common-mode output voltage can be fixed with the aid of a common-mode input current.

Over-all common-mode feedback.#

Over-all common-mode feedback uses the balanced stage to be biased as part of the circuit that controls the common-mode voltage at one of its ports. Fig. 515 shows the application of overall-feedback for fixing the common-mode voltage at the input port of an anti-series CS stage. The common-mode voltage at the sources of the differential pair (M1, M2) is used to control the input common-mode current generated by M3 and M4. The input common-mode voltage is set to the sum of the gate-to-source voltages of (M1, M2) and (M3, M4). These voltages are defined by the technology the geometry and the drain currents of the MOS transistor.

Fig. 516 gives an arrangement in which the common-mode voltage at the output of the differential pair is also fixed by using over-all common-mode feedback. This voltage equals the sum of the gate-to-source voltages of (M5, M6) and M7. The anti-series CD stage constructed with M5 and M6, detects the common-mode voltage at the output of the anti-series stage (M1, M2) and adds a voltage level shift to it. In order to keep the differential-mode to common-mode conversion low, the pair (M5, M6) should operate in strong inversion.

It should be noted that common-mode feedback may result in common-mode instability and frequency compensation techniques may be required to ensure frequency stability of the common-mode loop(s). In general, the bandwidth of the common-mode loop should be kept as large as possible. Bandwidth reduction of the common-mode loop, combined with differential to common-mode conversion may result in operating point shift and reduction of overdrive recovery. The design of the frequency behavior of the common-mode behavior proceeds similar to that of the differential-mode behavior.

../_images/diffPairNMOSfixInOutCmValt.svg — Fig. 515 Anti-series CS stage of which the common-mode input voltage is fixed using over-all common-mode feedback, while the common-mode voltage of the output port is fixed with the aid of local common-mode feedback.#

../_images/diffPairNMOSfixInOutCmValtInOut.svg — Fig. 516 Anti-series CS stage of which the common-mode input and output voltages have been fixed using over-all common-mode feedback.#

Biasing of complementary-parallel stages#

In this section, we will discuss the biasing of the balanced complementary parallel stages. In Chapter Balancing techniques, we have seen that these stages can be biased with common-mode voltage sources only (see Fig. 208).

../_images/complParlBasicBias.svg — Fig. 517 Biasing of the complemantary parallel stage: A. Biasing scheme according to Fig. 208#

B. Biasing using nonlinear resistors with a current source and a voltage source character.

Fig. 517 shows the biasing of the complementary parallel stage. Fig. 517A shows the initial biasing scheme from Fig. 208. Fig. 517B shows the biasing with two supply sources and nonlinear resistors with a voltage source or current source character. Because of its importance as class AB output stage in operational amplifiers, the biasing of the complementary parallel stage has been a subject of research and many solutions have been proposed. The most important aspects related to the design of the biasing of the complementary parallel stage are:

Accurately fixing of the quiescent current over a wide temperature range and supply voltage range.

In order to make the quiescent (common-mode) current of the stage constant over a wide supply range and temperature range, the voltages of V3 and V4 should accurately track with the supply voltages and with the gate-to-source voltages of the MOS transistors.
Minimization of the cross-over distortion of the stage.

If the complementary parallel stage operates in class AB mode, the transfer during the zone in which the two transistors contribute equally to the output current may strongly differ from the transfer in the regions in which either the P or the N device contributes to the output current. This behavior has already been illustrated in Fig. 210. This change in gain during the take-over of the current causes so-called cross-over distortion. Minimization of this distortion requires optimization of the quiescent current of the complementary-parallel stage.

In this section we will present three solutions for the biasing of the complementary parallel stage. All solutions use model-based biasing techniques.

First we will introduce a low-voltage solution in which the power supply defines the biasing current. Secondly, we will present a solution for a complementary parallel stage that can be biased from a higher voltage and driven from a single input signal. Subsequently we will present a solution for the biasing of a class AB output stage in which the P device and the N device are driven from separate signals.

Examples of implementations will be given for MOS technology only.

As stated earlier, the design of class AB output stages has been a topic of intensive research. The reader is invited to study literature on this subject, investigate the concepts behind circuit implementations and find alternative implementations of those concepts.

Model-based biasing of the CMOS inverter#

Fig. 518 shows a CMOS complementary-parallel CS stage, of which the transistors are biased at zero drain-gate voltage. The quiescent current of the stage is determined by the power supply voltages. Hence, for accurate biasing at an operating point with minimized cross-over distortion, the supply voltages should track with the quiescent gate-source voltages. This can be done with the aid of a low-drop voltage regulator as shown in Fig. 519. In the circuit shown in this figure, the total supply voltage $V_{S G_{P}} + V_{G S_{N}}$ is generated by letting the required bias current $I_{b i a s}$ flow through the series connection of an NMOS and a PMOS with shorted gate-drain.

Model-based biasing with single input signal#

Fig. 520A shows the concept of the common-mode biasing of a complementary parallel stage CMOS stage using biasing with two floating voltage sources (V1, V2). In order to make the quiescent current of this stage independent of the temperature and insensitive for device tolerances, the voltages of these sources should track with the quiescent gate-to-source voltages of the MOS devices. This can be achieved using model-based biasing.

In the CMOS implementation of this biasing concept, from Fig. 520B this is done by generating the reference current with two complementary MOS devices (M3, M5), biased at zero drain-to-gate voltage. Their quiescent operating conditions are copied to (M4, M6). Hence, the voltages across the two resistors (R2, R3) equal $V_{P -} V_{S G_{P}}$ and $V_{N} - V_{G S_{N}}$ , respectively. If all N devices are equal, and all P devices are equal, the quiescent current of all complementary pair are equal. They do, however, depend on the power supply voltage.

../_images/complParlBiasRmod.svg — Fig. 520 Model-based biasing of the complemantary parallel stage: A. Biasing concept B. Model-based CMOS implementation.#

Low-voltage push-pull stage biasing#

A similar biasing method can be used for biasing a complementary-parallel stage at low supply voltages. We speak of low-voltage design if the power supply voltage can be as low as the sum of one gate-to-source or base-to-emitter voltage and one drain-to-source or collector-to-emitter saturation voltage.

A. Torralba, R. G. Carvajal, J. Ramirez-Angulo, J. Tombs and T. Galan \cite[-2.2cm]{Torralba2001}, present a solution for low-voltage biasing of a complementary-parallel stage of which the concept is shown in Fig. 521.

In the right part of the circuit, the transistors M3 and M4, together with the resistor R2 that implements a floating voltage source and the power supply source V1, constitute the biased complementary parallel stage. The voltage across R2 is generated by two controlled current sources of which the current is a copy of the output current of the controller in the bias control circuit. This bias control circuit is shown left from the dashed line. This circuit generates the current $I_{N}$ that will cause a voltage drop of $V_{S G_{P}} + V_{G S_{N}} - V_{P}$ across a resistor with a resistance $R$ , where $V_{S G_{P}}$ and $V_{G S_{N}}$ are the diving voltages for letting the PMOS and the NMOS operate at a quiescent current $I_{b i a s}$ . This is achieved as follows.

../_images/complParlBiasRmodLowVoltage.svg — Fig. 521 Low-voltage model-based biasing of the complemantary parallel stage.#

The required bias current $I_{b i a s}$ is generated by the reference current source I1. This current flows through the gate-drain shorted PMOS, while a copy of it flows through the gate-drain shorted NMOS. In this way the two driving voltages for the MOS transistors $V_{S G_{P}}$ and $V_{G S_{N}}$ are obtained.

In order to create a voltage drop $V_{S G_{P}} + V_{G S_{N}} - V_{P}$ across a resistor, R1 is tied to node (1) and a nullator is placed between node (2) and (3). The norator draws a current $I_{N}$ through R1, which causes the required voltages drop across it. In order not to affect the current trough M1, a copy of the norator current is delivered by I3. In this way, the current $I_{N}$ causes the required voltage drop $V_{S G_{P}} + V_{G S_{N}} - V_{P}$ across R1. The controlled current sources I4 and I5 provide a copy of this current for biasing M3 and M4 at a quiescent current $I_{b i a s}$ .

It should be noted that the location of the norator and the current-controlled current source I3 can be interchanged. This also holds for I1 and I2.

Model-based biasing with split input signal#

../_images/Montichelli.svg — Fig. 522 Output stage with split signal path for source and sink output current, presented by Montichelli.#

Fig. 522 shows a solution presented by Monticelli\cite[-10cm]{Monticelli1986} that uses a so-called split signal path. The circuit consists of two amplifier halves, one providing the source output current and the other providing the sink output current. The source and the sink current are added by connecting the outputs of the source and the sink halves in parallel.

Fig. 522A shows the basic concept. The controlled current sources (I1, I2) provide the signal current, while the bias voltages provided by V1 and V2 and the bias currents provided by I3 and I4 set the quiescent current of the output complementary CS stages (M2, M4). A positive signal current provided by I1 causes a sink output (signal) current, while a positive signal current provided by I2 causes a source output (signal) current. The signal currents from (I1, I2) are passed through the common-gate stages (M1, M3) to the output transistors (M2, M4), respectively.

Fig. 522B shows the implementation in which the current source element I5, together with M5 through M8 provide the model-based biasing voltages for the transistors in the signal path.

As a result of the inclusion of the common-gate stages in the signal path, circuit is not a true complementary-parallel connection of CS stages. Fig. 523A shows the simplified signal diagram with generic biased devices and Fig. 523B shows the small-signal equivalent circuit.

../_images/smallSignalMontichelli.svg — Fig. 523 Signal diagram and small-signal equivalent circuit of the push-pull stage from Fig. 522A.#

Fig. 523A shows that if the two inputs are connected together, the stage acts as complementary-parallel CS stage. For non-zero frequencies this can be achieved by placing a capacitor across the two input terminals.

In the quiescent operating point both the push and the pull stage contribute to the output current. If both stages have equal parameters, the controlled current sources G1 and G3 generate equal but opposite currents and the resistors R1 and R3 carry no voltage. The stage then acts as a parallel connection of two complementary CS stages.

In cases in which the output source or sink current exceeds the quiescent bias current, only the source or sink output transistor contributes to the output current.

Fig. 524 shows the signal diagram and the small-signal equivalent circuit for the sink or the source phase. During the sink phase M1 and M4 are active, while during the source phase M3 and M2 are active. The stage then acts as a cascade connection of a common-gate and a common-source stage.

Setting up the initial biasing scheme

Contents

Setting up the initial biasing scheme#

CE and CS stage biasing#

Biasing of local-feedback stages#

Setting up the initial biasing scheme of CD and CC stages#

Setting up the initial biasing scheme of CG and CB stages#

Initial biasing of other three-terminal configurations#

Biasing of cascode stages#

Biasing of anti-series stages#

Source or load common-mode biasing#

Brute force common-mode biasing#

Local common-mode feedback#

Feed forward common-mode biasing#

Over-all common-mode feedback.#

Biasing of complementary-parallel stages#

Model-based biasing of the CMOS inverter#

Model-based biasing with single input signal#

Low-voltage push-pull stage biasing#

Model-based biasing with split input signal#