MOS transistors#
The Metal Oxide Semiconductor Transistor was invented by Kahng and Dawon in 1959: [33]. The first CMOS circuit has been reported in 1963 by Wanlass and Sah (see [34]).
MOS Transistors are field effect devices with their gate isolated from the channel by SiO\(_{\text{2}}\). Aluminium and polysilicon are commonly used as gate materials. Depending on their application MOS transistors are fabricated in different ways:
Standard IC CMOS devices are lateral devices with a symmetrical structure: the source and the drain can be interchanged.
Modern IC Fin FET devices have a three dimensional gate structure that almost completely surrounds the channel.
High-voltage MOS transistors can be fabricated as lateral devices or as vertical devices. They are strongly asymmetrical: the low-voltage gate-source structure differs from the high-voltage gate-drain structure.
MOS transistors found their first application in digital circuits. Although bipolar and BiCMOS
IC processes are still in use, high-volume analog ICs and mixed signal ICs
are nowadays predominantly fabricated in CMOS technology.
Power MOS transistors are available in high-voltage IC processes and as discrete devices. They are mostly used as power switches in switched regulators and switched amplifiers.
Fig. 101 shows a simplified cross section of P-substrate C-MOS (complementary MOS) process as well as the device symbols for NMOS and PMOS transistors.
Fig. 101 Cross section of a standard CMOS integrated circuit process.#
Operation#
We will describe the basic MOS operation for the NMOS from Fig. 101. We will assume that the source and the bulk (substrate) of the NMOS have been connected to a reference potential (\(0\)V), while the drain has been connected to a fairly large positive voltage \(V_{DS}\). For this set up, we will briefly describe the relation between the drain-source current \(I_{DS}\) and the gate-source voltage \(V_{GS}\).
With \(V_{GS}=0\) the potential at the interface between the oxide and p-doped substrate is defined by the built-in junction voltage and the oxide capacitance.
At small values of \(V_{GS}\), due to capacitive coupling with the gate, this so-called surface potential almost linearly increases with \(V_{GS}\) and the source starts injecting electrons in the p-region. The electrons injected in the p-region start to form an n-type channel under the gate and we speak of weak inversion. These electrons reach the accelerating electrical field of the drain depletion layer through diffusion. They are collected at the drain terminal. As a result the \(I_{DS}\left( V_{GS}\right) \) characteristic shows an exponential relationship comparable with that of the \(I_{C}\left( V_{BE}\right) \) relationship of a lateral bipolar NPN transistor.
At increasing values of \(V_{GS},\) the channel extends further under the gate, and the surface potential does no longer increase significantly with the gate-source voltage. The drain current now increases quadratically with the difference between \(V_{GS}\) and the so-called threshold voltage \(V_{T} \), just as with the JFET. The device now operates in strong inversion. The threshold voltage \(V_{T}\) is defined as the gate-source voltage at which the transition from weak inversion to strong inversion takes place.
As long as the effective gate-source voltage \(V_{GS}-V_{T}\) is below \(V_{DS},\) the channel does not extend to the drain. In this pinch-off or saturation region the drain-source current only shows a minor dependency of \(V_{DS}\) due to the channel length modulation, an effect comparable to the Early effect in bipolar transistors.
If \(V_{GS}\) increases to a level of \(V_{T}\) above \(V_{DS}\) the channel extends from the source to the drain and \(I_{DS}\) becomes strongly dependent on \(V_{DS}\) as well. The transistor then acts as a voltage-controlled resistor and we speak of the linear operating region.
Small geometry effects#
The basic operation described above holds for large MOS transistors. However, with shrinking dimensions in CMOS IC processes, small geometry effects have to be taken into account. Below a listing of the most important small-geometry effects.
With shrinking oxide thickness, the influence of the vertical component of the electrical field in the channel on the charge carrier mobility cannot longer be ignored. This field influences the vertical current density profile. A high vertical field causes a reduction of the mobility of the electrons moving horizontally from the source to the drain.
A shrinking channel length also results in an increase of the lateral electrical field. At high field strengths the velocity of the charge carriers saturates.
The electrical field in the gate increases with shrinking oxide thickness. This causes a slow change of charge storage in the oxide over time and results in a slow change of \(V_{T}\) over time. This effect may limit the operational life time of CMOS ICs.
In large MOSFETs the channel length modulation is the main contributor to the \(V_{DS}\) dependency of \(I_{DS}\). In short-channel MOSFETs the depletion region of the drain reaches far and deep under the channel and reduces the channel to bulk depletion capacitance under the channel. This improves the coupling between the gate-source voltage and the surface potential. This drain-induced barrier lowering (DIBL) effect causes \(V_{T}\) to decrease with \(V_{DS}\). As a result \(I_{DS}\) increases with \(V_{DS}\).
MOSFET modeling#
MOS transistors found their first application in digital circuits. Adequate simulation of these digital circuits could be preformed with relatively simple simulation models. Nowadays MOS transistors are also applied in analog integrated circuits, which requires an accurate description for all possible operating conditions.
The behavior of MOS transistors strongly depends on both their geometry and their manufacturing technology. The rapid development of new IC technologies and the reduction of dimensions continuously present new challenges to MOSFET modeling. For a complete description of MOSFET models including references to publications about underlying physical mechanisms the reader is referred to literature. Foty describes the following models(see [35]):
The Level 1 model is usually referred to the model presented by Shichman and Hodges (see [32]). This is a relatively simple first generation MOS model for thick-oxide, long and wide channel MOSFETs, operating in strong inversion. It can be used if simulation speed is more important than accuracy. Due to its low complexity, this model can also be used as a basis for hand calculations.
The Level 2 model is also a first generation model. It is based on the Level 1 model. Corrections are in the form of additional equations that account for small-geometry effects. They make the model mathematically complex and inefficient.
The Level 3 model is also based on the Level 1 model, but the added equations that account for small-geometry effects have a more empirical character. They use less parameters and are more simple than those of the Level 2 model. The Level 3 model also includes basic modeling of operation in weak inversion.
The BSIM (Berkeley Short-Channel IGFET Model, see [36] ) is a second generation MOSFET model. The model has its focus on fast and robust simulation rather than on a physical basis.
The HSPICE Level 28 model is a second generation model based on the BSIM model (see [37]). Its improvements strongly facilitated analog CMOS circuit design. It is a proprietary model developed by Meta-Software.
The BSIM2 model is also a second generation MOSFET model. It is an improvement of the BSIM model developed by the university of Berkeley.
The BSIM3 model is a third generation model (see [12]). Second generation models are constructed with an extrinsic model on top of the intrinsic model structure. The third generation BSIM3 model has its geometry parameters included the intrinsic model.
The MOS Model 9 is a third generation MOS model developed at Philips Laboratories that has been made generally available (see \cite[-0.5cm]{MOS9}). The modeling approach differs from the approach taken in the development of the BSIM3 model. The MOS Model 9 still distinguishes an intrinsic and an extrinsic structure, but it has improved mathematical modeling.
The EKV model (see [13]) has a physical base and is oriented on low-power analog design. It differs from other third generation models because it takes the bulk node as reference rather than the source node. Source and drain are treated equally, yielding a symmetrical model with smooth analytical equations for all operating regions. Hence, it is very well suited for analog design simulation.
The BSIM4 model is suited for analog CMOS design in technology nodes below 100nm (see [38]).
In the following sections only a selection of the above models will be discussed. Due to its relative simplicity, the Level 1 model can be used as a basis for hand calculations for devices working in strong inversion in the saturated and in the linear operating region. We will discuss the model in section MOSFET level 1 model.
The Level 1 model is not accurate enough to predict the behavior of analog CMOS circuits in modern sub micron technology. In modern IC design predominantly BSIM3, BSIM4 and MOS Model 9 are used. Because of their complexity they are not very well suited for hand calculations. For hand calculations of the voltage and current handling capabilities of MOS transistors, the Level 1 is still widely used. In section Capacitance models we will confine ourselves to a brief discussion of small-signal models and model data obtained from simulation with some of these models.
More attention will be paid to the EKV model. The physical bases of this model with smooth analytical expressions that cover all operating conditions, makes them very well suited for deriving design information at early stages of the design. Binkley describes the application of the EKV model, and particularly, the use of the inversion coefficient, for taking design decisions (see [14]).
The symbolic simulator SLICAP uses small-signal models of which the parameters are related to the device geometry and the inversion coefficient. Both the basics and the application of the EKV model will be discussed in section MOS EKV Model.
MOSFET level 1 model#
Fig. 102 SPICE MOSFET model#
Fig. 102 shows the level 1 MOSFET model as it is implemented in SPICE. The model consists of a four-terminal intrinsic MOS transistor and two bulk resistances in series with the intrinsic transistor. Some SPICE versions support bulk resistances for the gate and the bulk connections. Some geometrical arguments can be given to the MOS model (see the SPICE reference manual). We will give an overview of these arguments and the parameters in section Device parameters. The expressions are given for N-channel MOSFETs.
Instantaneous behavior#
The gate and bulk currents for all operating conditions are given by the diode currents:
if JS\ \(=0\), AS\ \(=0\), or AD\ \(=0\) (AS and AD are arguments for the drain and source areas, respectively) we have
else:
where IS and JS represent the drain-bulk and source-bulk junction saturation current and current density, respectively. The bulk resistances can be modeled with geometrical arguments:
or without geometrical arguments:
The model equations of the controlled source \(I_{ds}\) differ for the various operating regions:
Normal mode \((V_{d^{\prime}s^{\prime}}>0),\) cut-off region: \(V_{gs^{\prime}}-V_{to}<0;\) the cut-off voltage \(V_{to}\) depends on the bulk-source or\ back-gate\ voltage:
\[V_{to}=\text{VTO}+\text{GAMMA}\left( \sqrt{\left( \text{PHI}-V_{bs^{\prime}}\right) }-\sqrt{\text{PHI} }\right) ,\]while
\[I_{ds}=0.\]Normal mode \((V_{d^{\prime}s^{\prime}}>0),\) linear region: \(V_{d^{\prime}s^{\prime}}<V_{gs^{\prime}}-V_{to}\), or, alternatively: \(V_{dg^{\prime}}<-V_{to}\)
(29)#\[I_{DS}=\frac{\text{W}}{\text{L}}\text{KP}\left( 1+\text{LAMBDA.}V_{d^{\prime}s^{\prime}}\right) V_{d^{\prime }s^{\prime}}\left( \left( V_{gs^{\prime}}-V_{to}\right) -\frac{V_{d^{\prime}s^{\prime}}}{2}\right) . \label{eq-IdMOSlin}\]Normal mode \((V_{d^{\prime}s^{\prime}}>0),\) saturation region: \(0\leq V_{gs^{\prime}}-V_{to}\leq V_{d^{\prime}s^{\prime}}\), or, alternatively: \(V_{dg^{\prime}}>-V_{to}\)
(30)#\[I_{DS}=\frac{\text{W}}{\text{L}}\frac{\text{KP}}{2}\left( 1+\text{LAMBDA.}V_{d^{\prime}s^{\prime}}\right) \left( V_{gs^{\prime}}-V_{to}\right) ^{2}. \label{eq-IdMOSsat}\]Reverse mode \((V_{d^{\prime}s^{\prime}}<0)\)
For reverse mode operations the drain and the source connections are swapped.
If not given, the transconductance factor KP is obtained from geometrical input parameters and physical constants:
in which \(\epsilon_{ox}\) is the permittivity of SiO\(_{2}\), which is about \(34\times10^{-12}\)F/m. The factor \(10^{-4}\) is a consequence of the units given to the surface mobility UO: cm\(^{2}\)/Vs. If we define \(C_{ox}\ \)as\(\ \)the oxide capacitance per unit of area:
the transconductance factor can alternatively be written as
In IC design manuals, the MOS transconductance factor KP is often denoted as \(\beta_{sq}\). Modern low-voltage MOS processes can have \(\beta _{sq}\) values larger than \(100\times10^{-6}\)A/V\(^{2}\).
Dynamic effects#
The dynamic behavior of the MOS transistor is modeled with the capacitances from Fig. 102. The input capacitance \(C_{gs^{\prime}}\) is the sum of the gate-source overlap capacitance \(C_{gso}\) and a portion of the oxide capacitance. The latter one depends on the operating mode of the MOS. In the linear operating range it is \(\frac{1}{2}C_{ox}\) and in the saturation region it amounts \(\frac{2}{3}C_{ox}.\)
The capacitance \(C_{gd^{\prime}}\) also depends on the mode of operation. In the linear operating range it is \(\frac{1}{2}C_{ox}+C_{gdo}\) and in the saturation range it equals the gate-drain overlap capacitance \(C_{gdo}\). The gate-source overlap capacitance \(C_{gso}\) and the gate-drain overlap capacitance \(C_{gdo}\) depend on the device width:
The gate-bulk capacitance \(C_{gb}\) also depends on the operating mode. In this model it is determined by the bulk-gate overlap capacitance:
The source-bulk and drain-bulk depletion capacitances depend on the junction voltages:
If no geometrical arguments are given, W and L have their default values and the model equations for these capacitances are:
Small-signal equivalent circuit#
The small-signal equivalent circuit of the MOSFET\ is shown in Fig. 103. It consists of the five capacitances, two linear controlled sources and the bulk resistances.
Fig. 103 Small-signal equivalent circuit of a MOS transistor.#
The transconductances of the controlled sources are defined as
The capacitances are according to the definitions above. The output resistance \(r_{d^{\prime}s^{\prime}}\) is defined as
The values of the bulk resistances are obtained according to expression (27)\ to (28).
Stationary noise model#
A frequency domain noise analysis can be performed in SPICE. For this purpose, stationary noise sources are added to the small-signal equivalent circuit from Fig. 103. This stationary noise model is shown in Fig. 104.
Fig. 104 Small-signal equivalent circuit of a MOS transistor with added noise sources.#
The thermal noise of the two bulk resistors \(R_{s}\) and \(R_{d}\) is given by their voltage spectral densities \(S_{vs}\) and \(S_{vd}\), respectively:
The noise related to the channel current shows a \(\frac{1}{f}\) component:
This can also be denoted as
where \(f_{\ell}\) is the corner frequency for the \(\frac{1}{f}\) noise. The cut-off frequency strongly depends on the technology and can exceed \(1\) [MHz].
Device parameters#
Geometrical scaling factors#
Table 13 shows the geometrical scale factors for MOS devices.
name |
description |
unit |
default |
W |
channel width |
m |
\(10^{-4}\) |
L |
channel length |
m |
\(10^{-4}\) |
AD |
drain area |
m\(^{2}\) |
\(0\) |
AS |
source area |
m\(^{2}\) |
\(0\) |
PD |
perimeter of drain junction |
m |
\(0\) |
PS |
perimeter of source junction |
m |
\(0\) |
NRD |
number of squares drain diffusion |
\(0\) |
|
NRS |
number of squares source diffusion |
\(0\) |
|
Model parameters instantaneous behavior#
The MOS model parameters that describe the instantaneous behavior are listed in Table 14.
name |
description |
unit |
default |
note |
VTO |
pinch-off voltage |
V |
\(0\) |
1 |
KP |
transconductance factor |
A/V\(^{2}\) |
\(2\times10^{-5}\) |
1 |
LAMBDA |
channel length modulation coeff. |
1/V |
\(0\) |
|
PHI |
surface potential |
V |
\(0.6\) |
1 |
GAMMA |
bulk threshold parameter |
V\(^{1/2}\) |
\(0.0\) |
1 |
RD |
drain bulk resistance |
\(\Omega\) |
\(0\) |
1;2 |
RS |
source bulk resistance |
\(\Omega\) |
\(0\) |
1;2 |
RSH |
drain and source sheet resistance |
\(\Omega/\square\) |
||
IS |
bulk junction saturation current |
A |
\(10^{-14}\) |
1 |
JS |
bulk junction sat. current density |
A/m\(^{2}\) |
\(0\) |
|
TNOM |
nominal temperature |
\(^{\text{o}}\)C |
\(27\) |
|
note 1 |
{overrides results from process and geometry input} |
|||
note 2 |
{either resistance; or resistance per unit of channel width} |
|||
Model parameters dynamic behavior and noise#
Additional parameters that are required for the description of a MOSFET’s dynamic behavior are listed in Table 15.
Process parameters#
The process parameters are used to calculate the instantaneous model parameter values. For the relations between the process parameters and the instantaneous model parameters we refer to the literature. These parameters are listed in Table 16.
name |
description |
unit |
default |
CGSO |
gate-source overlap capacitance per meter channel width |
F/m |
0 |
CGDO |
gate-drain overlap capacitance per meter channel width |
F/m |
0 |
CGBO |
gate-bulk overlap capacitance per meter channel length |
F/m |
0 |
CBD |
zero-bias bulk-drain capacitance |
F |
0 |
CBS |
zero-bias bulk-source capacitance |
F |
0 |
CJ |
zero-bias bulk bottom capacitance per area |
F/m\(^{2}\) |
0 |
PB |
built-in gate junction potential |
V |
0.8 |
MJ |
bulk junction bottom grading coefficient |
||
MJSW |
bulk junction sidewall grading coefficient |
||
CJSW |
zero-bias bulk-junction sidewall capacitance |
||
FC |
forward bias depletion capacitance coefficient |
V |
0.5 |
AF |
flicker noise exponent |
1 |
|
KF |
flicker-noise coefficient |
0 |
|
Cut-off frequency#
The cut-off frequency \(f_{T}\) of a MOSFET is defined as the unity-gain frequency of the current gain factor:
where \(C_{iss}\) is the total input capacitance with shorted output:
name |
description |
unit |
default |
TOX |
gate oxide thickness |
m |
\(10^{-7}\) |
NSUB |
substrate doping |
1/cm\(^{3}\) |
\(0\) |
NSS |
surface state density |
1/cm\(^{2}\) |
\(0\) |
TPG |
type of gate material: |
\(1\) |
|
+1: poly silicon; type opposite to substrate |
|||
-1: poly silicon; type same as substrate |
|||
\texttt{ 0}: Al gate |
|||
LD |
lateral diffusion |
m |
\(0\) |
UO |
surface mobility |
cm\(^{2}\)/Vs |
\(600\) |
UTRA |
transverse field coefficient |
\(0\) |
|
Operating point information#
Similar as with the BJT and the JFET, the current drive capability and the voltage drive capability of a MOS transistor depend on the DC drain current \(I_{D}\) and the drain-source voltage \(V_{DS}\). Many other performance aspects, such as the noise performance and the cut-off frequency, also show a direct relation with the drain current. As a consequence, we usually want to fix the operating point by means of fixing \(I_{D}\) and \(V_{DS}\).
A method for fixing the operating point of nonlinear resistive multi-terminal devices has been discussed in Chapter Amplification Mechanism. According to the presented method, fixing the operating point of a MOSFET by means of \(I_{D}\) and \(V_{DS}\) requires the addition a voltage source \(V_{DS}\) between the drain and the output and a current source \(I_{D}\) that flows from the source to the drain.
In order to obtain zero output voltage and zero output current for all DC input and output terminations, a voltage source \(V_{GS}\) has to be placed in series with the gate and a current source \(I_{G}\) has to be connected in parallel with the gate-source junction. The values of these input sources depend on the required values of \(I_{D}\) and \(V_{DS}\), on the DC characteristics of the device and on the operating temperature. They can be determined with the aid of the circuit from Fig. 105. The nullator at the output port (drain-source) sets the condition for zero output voltage and zero output current, while the norator at the input port delivers the correct driving quantities to satisfy these conditions. Although the nullor is not available in SPICE, it can be implemented with the aid of two unity-gain voltage-controlled voltage sources as illustrated in this figure.
Simplified models for hand calculations#
Complete SPICE models are suitable for numerical simulations but they are too complex to provide design information from analytical expressions. For this purpose we need simplified models that are suited for hand calculations. In this section we will derive such models. We will introduce a large signal static model, a small-signal dynamic model and a noise model that can be used for analytical determination of the operating point, the dynamic small-signal transfer and the noise behavior of a MOSFET. We will deal with the active forward region only.
DC behavior#
A DC model, suitable for hand calculations is depicted in Fig. 106. The diodes, the capacitances and the bulk resistances have been omitted and only the nonlinear voltage-controlled current source remains. The current of this controlled source depends on both the gate-source and the drain-source voltage. The bulk is connected to the source, hence the threshold voltage \(V_{to}\) is not affected by \(V_{bs}\). Different relations exist for the cut-off region, the linear region and the saturation region.
Normal mode \((V_{ds}>0),\) cut-off region: \(V_{gs}-\)VTO\(<0,\) we have
\[I_{ds}=0.\]Normal mode \((V_{ds}>0),\) linear region: \(V_{ds}<V_{gs} -\text{VTO}\), or, alternatively: \(V_{dg}<-\text{VTO}\)
\[I_{ds}=\frac{\text{W}}{\text{L}}\text{KP} V_{ds}\left( V_{gs}-\text{VTO}\right) \left( 1+\text{LAMBDA.}V_{ds}\right) .\]Normal mode \((V_{ds}>0),\) saturation region: \(0\leq V_{gs} -\text{VTO}\leq V_{ds}\), or, alternatively: $V_{dg}
-\text{VTO}$
\[I_{ds}=\frac{\text{W}}{\text{L}}\frac{\text{KP}}{2}\left( V_{gs}-\text{VTO}\right) ^{2}\left( 1+\text{LAMBDA.}V_{ds}\right) .\]Reverse mode \((V_{ds}<0)\)
For reverse operation, the drain and the source connections are swapped.
Small-signal dynamic behavior#
The simplified small-signal dynamic model for a source-bulk connected MOSFET is shown in Fig. 107.
The model parameters can roughly be determined from the Level 1 device model, the geometry parameters and the operating voltages and currents. These approximations are shown in Table 17.
par. |
cut-off. |
linear region |
saturation region |
\(C_{gs}\) |
CGSO.W\(+\)CGBO.L\(+\) |
CGSO.W \(+\)CGBO.L\(+\) |
CGSO.W\(+\)CGBO.L\(+\) |
\(+\frac{\text{W.L}}{\text{TOX}}\epsilon_{ox}\)(max. value) |
\(+\frac{1}{2}\frac{\text{W.L}}{\text{TOX}}\epsilon_{ox}\) (max. value) |
\(+\frac{2}{3} \frac{\text{W.L}}{\text{TOX}}\epsilon_{ox}\) (max. value) |
|
\(C_{gd}\) |
CGDO.W |
CGDO.W\(+\) |
CGDO.W |
\(+\frac{1}{2}\frac{\text{W.L}}{\text{TOX}}\epsilon _{ox}\) (max. value) |
|||
\(C_{ds}\) |
CJ.AD\(+\)CJSW.PD or CBD |
CJ.AD \(+\)CJSW.PD or CBD |
CJ.AD\(+\)CJSW.PD or CBD |
\(g_{m}\) |
\(0\) |
\(\frac{\text{W}}{\text{L}}\).KP \(V_{DS}\) |
\(\frac{\text{W}}{\text{L}}\).KP\(\left( V_{DS}-\text{VTO}\right) =\) |
\(=\sqrt{2\frac{\text{W}}{\text{L}}\text{.KP }I_{DS}}\) |
|||
\(r_{ds}\) |
\(\infty\) |
\(\left[ \frac{\text{W}}{\text{L} }\text{.KP}\left( V_{GS}-\text{VTO}\right) \right] ^{-1}\) |
\(1/(\)LAMBDA\(~I_{DS})\) |
voltage controlled resistor |
(LAMBDA \(\ll1\)) |
||
approximation (\(V_{DS}=0\)) |
|||
Noise model#
The simplified noise model is shown in Fig. 108. The bulk resistances \(R_{s}\) and \(R_{d}\) are omitted and the remaining noise sources are added to the simplified hybrid-\(\pi\) equivalent circuit from Fig. 107.
Fig. 108 Simplified small-signal equivalent circuit with noise sources of a bulk-source connected MOSFET.#
Determination of the hybrid-\(\pi\) parameters by a simulation#
If the small-signal parameters of a MOSFET are not provided by the simulator’s operating point analysis, they can be determined with the aid of a small-signal analysis. The procedure is similar to that of bipolar transistors as discussed in section Simplified models for hand calculations. Fig. 109 shows the simulation setup.
The procedure is as follows:
Bias the device in the required operating point with \(V_{GS}\) and \(V_{DS}\)
Add an AC signal (AC 1 0) to \(V_{AC1}\) only
Perform an AC analysis over the frequency range of interest
Obtain the following small-signal parameters
Now add the AC signal (AC 1 0) to \(V_{AC3}\) only
Perform an AC analysis over the frequency range of interest
Obtain the following small-signal parameters
\[\begin{split}g_{mb} & =\operatorname{Re}\left\{ I(V_{AC2})\right\} ,\\ C_{bs} & =-\frac{\operatorname{Im}\left\{ I(V_{AC1})\right\} }{2\pi f},\\ C_{bd} & =-\frac{\operatorname{Im}\left\{ I(V_{AC2})\right\} }{2\pi f}.\end{split}\]Now add the AC signal (AC 1 0) to \(V_{AC2}\) only
Perform an AC analysis over the frequency range of interest
Finally obtain the following small-signal parameters
\[\begin{split}g_{o} & =\frac{1}{r_{ds}}=-\operatorname{Re}\left\{ I(V_{AC2})\right\} ,\\ C_{dg} & =-\frac{\operatorname{Im}\left\{ I(V_{AC1})\right\} }{2\pi f}.\end{split}\]
In the following example, we will demonstrate the determination of the small-signal parameters of a biased NMOS that has its source connected to the bulk, by means of a SPICE simulation.
Example
Fig. 110 shows the simulation test bench for the determination of the small-signal parameters of an NMOS transistor.
Fig. 110 Simulation test bench for determination of the small-signal Y parameters of an NMOS transistor.#
The netlist, including the LTSPICE .measure statements for the determination of \(g_{m}\), \(g_{o}\), \(c_{iss}\), \(c_{oss}\), and \(c_{dg},\) has been listed below:
1YparHyPiPar.cir
2*LTspice netlist
3
4*Circuit for determination of Vgs
5M1 d1 Vgs 0 0 C18nmos L={L} W={W}
6V1 d1 o1 {Vds}
7I1 0 o1 {Ids}
8E1 Vgs 0 o1 0 1k
9
10*Circuit for determination of Y11 and Y12
11M2 d2 g2 0 0 C18nmos L={L} W={W}
12V2 d2 0 {Vds}
13V3 g2 i2 AC 1 0
14E2 i2 0 Vgs 0 1
15
16*Circuit for determination of Y21 and Y22
17M3 d3 g3 0 0 C18nmos L={L} W={W}
18V4 d3 0 {Vds} AC 1 0
19E3 g3 0 Vgs 0 1
20
21.lib CMOS18TT.lib
22
23.AC LIN 3 9.5Meg 10.5Meg
24
25* Device parameters
26.param W=220n L=180n
27
28* Operating point
29.param Vds=0.9 Ids=10u
30
31* LTspice specific instructions for printing the small-signal parameters (at f=10MHz) in dB:
32.meas AC g_m FIND Re(-I(V2)) AT 10MEG
33.meas AC g_o FIND Re(-I(V4)) AT 10MEG
34.meas AC c_iss FIND Im(-I(V3))/(2*pi*10meg) AT 10MEG
35.meas AC c_oss FIND Im(-I(V4))/(2*pi*10meg) AT 10MEG
36.meas AC c_dg FIND Im(I(E3))/(2*pi*10meg) AT 10MEG
37
The simulation results are printed in dB the LTSPICE output file (error log). The results are listed in the table below:
parameter |
dB value |
value |
units |
\(g_{m}\) |
\(-80.9417\) |
\(89.725\) |
\(\mu\)AV\(^{\text{-1}}\) |
\(g_{o}\) |
\(-109.767\) |
\(3.2483\) |
\(\mu\)AV\(^{\text{-1}}\) |
\(c_{iss}\) |
\(-305.649\) |
\(521.86\) |
aF |
\(c_{oss}\) |
\(-316.932\) |
\(142.36\) |
aF |
\(c_{dg}\) |
\(-317.011\) |
\(141.07\) |
aF |
From these values we find
and
Capacitance models#
One of the challenges of the modeling of the behavior of semiconductor devices is to translate the dynamic spacial charge distribution in the physical device, into a lumped element network model in which charge is concentrated on capacitances, while the dynamic currents in the device terminals depend on the changes of these charges. By using these techniques, effects of a limited carrier velocity cannot be accounted for accurately.
For an in depth treatment of this subject, the reader is referred to literature. Foty (see [35]) addresses two topics related with the modeling with lumped elements: charge conservation and the reciprocity of the capacitive elements. In this section we will simply introduce two capacitance models for the intrinsic MOS transistor without discussion of the underlying physical mechanisms.
Meyer model#
The model proposed by Meyer is commonly applied in the first generation MOS models (see [39]). The model assumes reciprocal capacitances \(\left( c_{dg}=c_{gd}\right) \). The model equations of the capacitances \(c_{gs^{\prime}},c_{gd^{\prime}}\) and \(c_{gb}\) differ for the linear region, the saturation region and the cut-off region.
The general implementation of the Meyer capacitance model is as follows:
In the linear region we have
In the saturation region the model equations are:
In the cut-off region we have:
Ward-Dutton capacitance model#
The Ward-Dutton capacitance model (see [11]), uses a capacitance matrix that relates the four dynamic terminal currents of the intrinsic transistor to the nodal voltages at the corresponding terminals. The capacitances are calculated from the charge equations of the MOSFET model. The resulting capacitance matrix is not necessarily reciprocal.
The matrix equation is
where \(i_{g},i_{d},i_{s}\) and \(i_{b}\) are the terminal currents of the intrinsic transistor, and \(v_{g},v_{d},v_{s}\) and \(v_{b}\) the nodal voltages at the corresponding terminals.
If the source and the bulk are connected together, and the source-bulk connection is taken as the reference node, this model simplifies to
The resulting model can be written in a form of which the equivalent hybrid-\(\pi\) network can be constructed:
The simplified hybrid-\(\pi\) equivalent circuit of the intrinsic transistor is found after addition of the static transadmittance \(g_{m}\) and the static output resistance \(r_{o}\). This circuit is shown in Fig. 111.
Fig. 111 Hybrid-\(\pi \) equivalent circuit of the intrinsic MOSFET according to the Ward-Dutton capacitance model.#
MOS EKV Model#
In this section, we will give a brief summary of the construction and the use of the EKV MOS model. The model is developed by Enz and Vittoz: [13]. The application of the model and especially the use of the inversion coefficient as basis for early stage design decisions, is extensively described by Binkley (see [14]). Expressions in this section involving the inversion coefficient have been taken from Binkley, but adapted in such a way that they can be used for estimation of the small-signal parameters of the hybrid-\(\pi\) equivalent model for all modes of operation.
Fig. 112 illustrates the basic idea behind the static model of the intrinsic MOS: the drain-source current is the sum of a forward and a reverse component. Both components \(I_{F}\) and \(I_{R}\) have smooth expressions with a validity range that covers weak inversion through strong inversion, including velocity saturation. The bulk node has been taken as reference node.
The expressions for \(I_{R}\) equal those for \(I_{F}\) after swapping \(V_{D}\) and \(V_{S}\). This makes the model symmetrical for the forward and reverse operation. The current equations are based upon the charge equations of the model.
In this section, we will briefly discuss the modeling of the \(I_{DS}\left( V_{GS},V_{DS}\right) \) characteristic for the different operating regions, introduce the inversion coefficient and relate the parameters of the small-signal model to the operating point, the technology parameters and the device geometry.
The technology current#
Binkley (see [14]) defines the technology current \(I_{0}\) as
where \(n\) is the substrate factor:
\(C_{DEP}^{\prime}\) is the surface depletion capacitance and \(C_{OX}^{\prime}\) is the oxide capacitance per unit of area:
where \(\varepsilon_{r}\) is the relative permittivity of SiO\(_{\text{2}}\), \(t_{ox}\) is the thickness of the gate oxide and \(U_{T}\) is the thermal voltage.
The reciprocal value of the substrate factor (\(\frac{1}{n}\)) models the coupling between the gate voltage and the surface potential at weak inversion.
The transconductance factor#
The transconductance factor \(\beta_{sq}\) is defined as
where \(\mu_{0}\) is the low-field channel carrier mobility in [m\(^{\text{2}} \)V\(^{\text{-1}}\)s\(^{\text{-1}}\)]. The technology current can be expresses in \(\beta_{sq}\) as
Weak inversion#
In weak inversion the drain-source current \(I_{F,R}\) shows an exponential relation with the gate voltage:
The voltage \(V_{T0}\) is the equilibrium threshold voltage. For \(V_{S}=0\) it corresponds with the threshold voltage \(V_{to}\) of the models discussed above.
Strong inversion#
When the device is operating in strong inversion, the drain-source current depends quadratically on the drive voltage:
where \(W\) and \(L\) are the effective width and length of the channel, respectively.
Weak inversion to strong inversion#
With the aid of a transition function \(F(x)\), the expressions for weak inversion and strong inversion can be combined into one:
\(\exp(x)\) |
\(\text{if }x\ll0;\) |
\(\left( \frac{x}{2}\right) ^{2}\) |
if \(x\gg0.\) |
This function returns the forward and the reverse inversion coefficient, \(IC_{F}\) and \(IC_{R}\), respectively:
These coefficients are a measure for the level of inversion at which the transistor operates. An inversion coefficient much smaller than unity indicates weak inversion. An inversion coefficient much larger than unity indicates operation in strong inversion. Between weak and strong inversion we speak of moderate inversion. The actual forward and reverse current can be calculated from the technology current, the device geometry and their respective inversion coefficients as:
or, alternatively:
Total drain-source current#
The total drain-source current \(I_{DS}\) is the difference between the forward and the reverse current (see Fig. 112):
When the transistor is operating in the saturation region, one of the current components \(I_{R}\) or \(I_{F}\) can be ignored with respect to the other.
Vertical field mobility reduction \#
The reduction of the mobility caused by the vertical field in the channel is modeled as reduction of the transconductance factor \(\beta_{sq}\) due to the gate-source voltage. A simple mobility reduction model uses the vertical field mobility reduction factor \(\theta\) [V\(^{\text{-1}}\)]
With this expression \(\beta_{sq}^{\prime}\)\ increases below threshold and has a singularity at \(\theta\frac{V_{G}-V_{T0}}{n}=-1\). This can be corrected by softly clipping the VFMR effect below threshold:
Channel length modulation and velocity saturation#
Channel length modulation and velocity saturation occur if the device is operating in the saturation region. In the SPICE EKV 2.6 model, the channel length modulation (CLM) and velocity saturation (VS) have been modeled through modification of the reverse current \(I_{R}\). For a full SPICE implementation of the EKV2.6 model the reader is referred to the EKV2.6 manual (see [40]). Both the velocity saturation and the channel length modulation can be modeled in a relatively simple way by ignoring their absence in the linear operating region. This will provide sufficiently accurate values for taking early stage design decisions.
Similar as with bipolar transistors, the channel length modulation can be modeled with an Early voltage. The Early voltage \(V_{A}\) is assumed proportional with the length of the device
where \(V_{AL}\) [Vm\(^{\text{-1}}\)] is the Early voltage per unit of length. After including the CLM in the expression of the drain-source current, \(I_{DS}\) changes to
Binkley (see [14]) describes the modeling of velocity saturation in the forward saturation operating region through introduction of a second term in \(\beta_{sq}\) ((37)):
where \(E_{CRIT}\) [Vm\(^{\text{-1}}\)] is the value of the lateral field at which velocity saturation occurs.
At a later stage we will use the critical inversion coefficient \(IC_{CRIT}\), which is defined as the inversion coefficient at which the reduction of the mobility due to VFMR and velocity saturation sets in:
It can be approximated by
Static device characteristics#
Fig. 113 shows the model with the source taken as reference node: \(V_{S}=0\) and \(V_{B}=0\).
Fig. 113 EKV model with the Source and Bulk connected togeter and taken as reference node.#
With the aid of this model we can find the \(I_{DS}\left( V_{GS} ,V_{DS}\right) \) characteristic for the linear and saturation region at strong inversion and compare them with those of provided by the Level 1 model.
In the saturation region, \(I_{R}\) can be ignored. If we discard the velocity saturation and the channel length modulation we can simplify ((38)) to the well known quadratic relation:
With \(V_{S}=0,\) this equation simplifies to the one the Level 1 model uses for the saturation region:
In the linear region, we cannot ignore the reverse current component and, under the above conditions, we may write
If \(V_{S}=0,\) this simplifies to the equation the Level 1 model uses for the linear region:
Fig. 114 shows the static device characteristics of an NMOS transistor myNMOS (\(W=220\)nm, \(L=180\)nm) calculated according to the above (simplified) model with parameters of a standard CMOS18 process as listed by Binkley (see [14]). The technology current for this device is \(634\)nA and the critical inversion coefficient \(IC_{CRIT}\) equals about \(41\). Hence, velocity saturation starts to play a role at about \(32\mu \)A. It should be noted that with this simple model of the channel length modulation and the velocity saturation, the characteristics are not accurate for short devices operating in the linear region.
Fig. 114 Device characteristics myNMOS, CMOS18 process. Left: Transfer characteristics \(I_{DS}\left(V_{GS},V_{DS}\right)\) Right: Output characteristics \(I_{DS}\left(V_{DS},V_{GS}\right)\)#
Linear and saturation region#
The transition from the linear to the saturation region occurs at \(V_{DS,sat} \):
For reverse operation \(V_{DS,sat}\) and \(IC_{F}\) should be replaced with \(V_{SD,sat}\) and \(IC_{R}\), respectively.
Small signal parameters#
Fig. 115 shows the small-signal model for the case that the source is taken as the reference node. Since the transconductance is defined at shorted output, we have \(v_{gs}=-v_{ds}\).
Fig. 115 Static small-signal model of the intrinsic MOS transistor with the source taken as reference node according to the EKV model.#
The forward small-signal transconductance \(g_{m}\) can be written as a function of the forward current and its associated inversion coefficient
The reverse transconductance \(g_{mR}\) can similarly be written as:
The total transconductance is found as the difference between the two:
Fig. 116 shows the transconductance as a function of the drain current of myNMOS.
Fig. 116 Device characteristics myNMOS, CMOS18 process. Left: \(g_m\) calculated from \(I_{DS}\) and the inversion coefficient according to ((41)). Right: \(g_ds\) calculated from \(I_{DS}\) and the inversion coefficient according to ((43)).#
In the forward operating range, the finite small-signal output conductance \(g_{ds}\) is caused by the channel length modulation and by \(g_{m_{R}}\):
In the saturation region, \(g_{mR}\) approximates zero and the output conductance is determined by the channel length modulation only. This part of the output conductance modeled in \(g_{o}\):
In the linear region \(g_{ds}\) equals \(g_{mR}\), however, expression ((40)) includes the effect of velocity saturation, which yields a too small value for the output conductance. A better estimate for \(g_{ds}\) in the forward linear operating range is:
Fig. 116 also shows the output conductance of myNMOS as a function of the drain current.
The body effect simply follows from \(g_{m}\) and \(n\) as
Transconductance efficiency#
The transconductance efficiency is defined as the ratio of the transconductance and the drain current. It is a measure for the transconductance produced per unit of drain current. The transconductance is used as a measure for the level of inversion. In weak inversion and in the saturation region, the transconductance efficiency has its largest value:
In strong inversion (without short channel effects) and in the saturation region, it drops to:
where \(V_{eff}=V_{GS}-V_{T0}\).
The transconductance efficiency of a MOS operating at an arbitrary inversion level in the forward saturation region, can be obtained from the inversion coefficient as:
Intrinsic capacitances#
The EKV2.6 manual gives expressions for the intrinsic small-signal capacitances (see \cite[-2cm]{spiceEKV2.6}). The small-signal dynamic model with these capacitances is shown in Fig. 117. A complete small-signal model requires addition of the extrinsic capacitances and the series resistances in the drain, the source and the gate.
The intrinsic capacitances can be expressed as a part of the total oxide capacitance \(C_{OX}\):
Fig. 117 Dynamic small-signal model of the intrinsic MOS transistor with the source taken as reference node according to the EKV model.#
The SPICE EKV2.6 model uses two parameters for calculation of these relative parts:
The intrinsic capacitances are
In the linear region, \(c_{gbi}\) drops to zero because it is completely covered by the conductive channel. The value of \(c_{gbi}\) below accumulation is not modeled.
The total input capacitance with shorted output \(c_{iss}\) is the sum of the three capacitances. The cut-off frequency \(f_{Ti}\) of the intrinsic transistor is defined as:
Fig. 118 Device characteristics myNMOS, CMOS18 process. Left: \(c_{gsi} \) plotted against \(V_{GS}\) with \(V_{DS}\) as parameter. Right: \(c_{gdi} \) plotted against \(V_{GS}\) with \(V_{DS}\) as parameter.#
Fig. 118 shows the plots of \(c_{gsi}\) and \(c_{gdi}\) against \(I_{DS},\) with \(V_{DS}\) as parameter. The plots
show that \(c_{gsi}\) rapidly increases from zero to \(\frac{2}{3}C_{OX},\) but it drops to \(\frac{1}{2}C_{OX},\) while \(c_{gdi}\) increases from zero to \(\frac{1}{2}C_{OX}\) when the device starts operating in the linear region.
Fig. 119 Device characteristics myNMOS, CMOS18 process. Left: \(c_{sbi} \) plotted against \(V_{GS}\) with \(V_{DS}\) as parameter. Right: \(c_{sbi} \) plotted against \(V_{GS}\) with \(V_{DS}\) as parameter.#
Fig. 119 shows the intrinsic source-bulk and drain-bulk capacitances, \(c_{sbi}\) and \(c_{dbi}\), respectively. These are parts of the junction capacitances under the channel, assigned to the source and the drain terminal.
Fig. 120 shows the plots of \(c_{gbi}\) and \(f_{Ti}\) against \(I_{DS}\) with \(V_{DS}\) as parameter.
Extrinsic capacitances#
The extrinsic capacitances have to be added to this intrinsic model. They consists of the overlap capacitances, the source-bulk junction capacitance and the drain-bulk capacitances. As a first approximation they can be modeled as in the Level 1 model.
Fig. 120 Device characteristics myNMOS, CMOS18 process. Left: \(c_{gbi} \) plotted against \(V_{GS}\) with \(V_{DS}\) as parameter. Right: The cut-off frequency of the intrinsic transistor \(f_{ti} \) plotted against the drain current with \(V_{DS}\) as parameter.#
Intrinsic noise model#
Fig. 121 shows the small-signal model of the intrinsic MOS transistor with added noise sources \(i_{g}\) and \(i_{d}\).
The spectral density \(S_{i_{g}}\) of \(i_{g}\) equals
where \(I_{G}\) is the DC gate (leakage) current. Flicker noise, associated with this noise source, can be modeled with the aid of a \(\frac{1}{f}\) corner frequency \(f_{\ell g}\):
Fig. 121 Dynamic small-signal noise model of the intrinsic MOS with the source taken as reference node according to the EKV model.#
The spectral density of \(i_{d}\) differs for the linear and the saturation region. In the linear region (\(V_{DS}<V_{DS,sat}\)) the spectral density \(S_{id}\) is that of a resistor with resistance \(\frac{1}{g_{o}}\):
where \(g_{o}\) can be\ written according to ((43)).
The spectral density \(S_{id}\) of the current noise associated with the drain current can be written as
where \(\Gamma\) equals \(\frac{1}{2}\) in weak inversion and \(\frac{2}{3}\) in strong inversion
. Binkley (see \cite[-0.5cm]{Binkley2008}) describes several expressions that model a smooth transition from weak inversion to strong inversion. The simplest function for \(\Gamma\) including VFMR and VS is:
Due to fluctuations in the carrier mobility, a flicker noise or \(\frac{1}{f}\) noise component is associated with the channel current. The spectral density of this noise current is
where KF [J] is the flicker noise coefficient. The corner frequency \(f_{\ell}\) is defined as the frequency at which \(S_{idf}=S_{id}\). With the aid of this corner frequency, the spectral density \(S_{id,tot}\) of the total noise current associated with the channel current can be written as:
The corner frequency \(f_{\ell}\) is obtained as:
If the transistor operates in the saturation region, the cut-off frequency \(\omega_{T}\) equals the ratio of \(g_{m}\) and \(\frac{2}{3}C_{OX}\). We then may write:
Hence, for a specific IC process the ratio between the flicker noise corner frequency \(f_{\ell}\) and the cut-off frequency \(f_{T}\) is constant. In a 180nm CMOS process with the transistor operating in the saturation region we have: \(n\approx1.35\), \(\Gamma=\frac{2}{3}\) and KF\(\approx4\times10^{-25}\) J. With these values we find \(f_{\ell}\approx\frac{f_{T}}{9000}\).
Summary#
Expressions for the parameters of the small-signal static model of the intrinsic MOS transistor operating in the saturation region have been described by Binkley (see [14]). Extension of the validity to the linear operating range is possible by using the both the forward and the reverse inversion coefficient. Full-range expressions for the small-signal intrinsic capacitances can be found in the EKV2.6 manual [40].
Modeling of the small-signal parameters with the forward and the reverse current requires the use of \(V_{GS}\) and \(V_{DS}\) as independent variables for the operating point. The use of the preferred output quantities \(I_{DS}\) and \(V_{DS}\) requires an iterative calculation process for resolving \(I_{DS}\) in a forward and a reverse component.