Conclusions#
In the previous sections, we investigated the criteria to achieve optimum noise performance with a CS stage for resistive and capacitive sources. We have seen that in general a low noise contribution comes at the cost of area and current consumption. For the lowest noise contribution, the CS stage should operate in the saturation region in strong inversion and with its optimum device width. However, such operation is not always required nor desired. If the noise addition of a CS stage can be designed well above its lower limit, both the costs for area and for current consumption can be reduced.
In general, the noise design proceeds as follows:
Check if the requirements are feasible as this has been done in the examples. If the requirements are not feasible, the noise requirement specification imposes a show stopper on the design and either it needs to be relieved or another CMOS process with better performance parameters should be selected.
If the noise requirements can easily be met, reduce the current and the device width in such a way that the noise requirements are met at lower cost factors, while some reserve has been built in for device tolerances and model inaccuracies.