23-11-2022: CS stage

Lecture: EE4109-4

Location: Pulse Hall 4

Time: 08:45 - 10:30

Quiz

SPICE test circuits

We will present two spice test circuits for the determination of properties of the intrinsic CS stage and the CS stage driven from and terminated with an parallel RC network.

• output voltage and current drive capability

• input voltage and current drive requirement

• input impedance and output impedance

• forward and reverse transfer parameters

• pole splitting

The biased CS stage

Introduction to the CS stage

The common-source stage is considered the basic amplifier stage in CMOS technology.

Presentation

The presentation “CS stage introduction” motivates the use of the CS stage as basic amplifier stage and summerizes the relevant performance aspects and design parameters of this stage.

Video

EE4109 2020 3_1: CS stage introduction.

The intrinsic CS stage

Presentation

The presentation Intrinsic CS stage: Design of static and dynamic performance discusses the design of the static (instantaneous) and the dynamic performance of a CS stage.

Videos

1. EE4109 2020 3_2: Intrinsic CS stage Determining Bias Sources.

2. EE4109 2020 3_3: Intrinsic CS stage V-I drive capability.

3. EE4109 2020 3_4: Intrinsic CS stage Small-signal dynamic performance:

4. EE4109 2020 3_5: Intrinsic CS stage Input and output impedance.

5. EE4109 2020 3_6: Intrinsic CS stage Geometry and current scaling.

Design of the static and dynamic performance of a CS stage between source and load

Demonstration

The design and analysis of the static and the dynamic behavior of the CS stage will be demonstrated with the LTspice and SLiCAP simulation tools.

Download SLiCAP-CSstage.zip and LTspice-CSstage.zip for running the analysis yourself.

Please upgrade to the latest version of SLiCAP_python: Version 1.0.1 before running the CS stage script.

Videos

1. EE4109 2020 3_7: Jupyter Notebook demo displaying device characteristics of CMOS18 transistors.

2. EE4109 2020 3_8: Static and the dynamic behavior of CS stage demonstrated with LTspice.

3. EE4109 2020 3_9: Static and the dynamic behavior of CS stage demonstrated with SLiCAP.

Group exercise

• Compare the Bode plots of the small-signal transimpedance factor of the biased CS stage operating in the active forward region, plotted with LTspice or ngspice using the BSIM model, and with SLiCAP using the EKV model. Use minimum geometry, VDS = 0.9V, and weak, moderate and strong inversion.

• Study the influence of geometry and inversion (discuss with each other, and verify)