26-11-2024: CS stage noise performance optimization

26-11-2024: CS stage noise performance optimization#

Lecture: EE4109-5

Location: Pulse Hall 7 (33.A2.200)

Time: 15:45 - 17:30

color coded resistors

Quiz#



Design of CS stage noise behavior#

Stationary noise model of the CS stage

Presentation

The presentation Intrinsic CS stage: Stationary noise model presents the stationary noise model of a CS stage.

Video

EE4109 2020 4_1 Intrinsic CS stage: Stationary noise model

Equivalent-input noise sources of a CS stage

Presentation

The presentation CS stage: Equivalent-input noise sources discusses the transformation of the channel noise into equivalent-input noise sources.

Video

EE4109 2020 4_2 Intrinsic CS stage: Equivalent-input noise sources

SLiCAP model of the equivalent-input noise sources of a CS stage

Presentation

The presentation CS stage: Equivalent-input noise sources - SLiCAP model presents the SLiCAP model of the equivalent-input noise sources of a CS stage.

Video

EE4109 2020 4_3 Intrinsic CS stage: Equivalent-input noise sources SLiCAP model

CS stage: Noise optimization with a resistive source

Presentation

The presentation CS stage: Noise optimization with a resistive source shows the way in which the noise contribution of a CS stage can be minimized for a resistive source. LTspice examples ans SLiCAP examples are available.

Download SLiCAP-CSstage.zip and LTspice-CSstage.zip for running the analysis yourself.

Videos

  1. EE4109 2020 4_4 CS stage: Noise optimization with a resistive source

  2. EE4109 2020 4_4a CS stage: Noise optimization with a resistive source; Spice Circuit

  3. EE4109 2020 4_6 CS stage: Noise SLiCAP

  4. EE4109 2020 4_7 CS stage: Noise LTSpice

CS stage: Noise optimization with a capacitive source

Presentation

The presentation "CS stage: Noise optimization with a capacitive source" shows the way in which the noise contribution of a CS stage can be minimized for a capacitive source.

Video

EE4109 2020 4_5 CS stage: Noise optimization with a capacitive voltage source

Group exercise#

important

Please follow the instruction below (in the given order)

  1. Install NGspice

  2. Update your SLiCAP installation from SLiCAP/SLiCAP_python.

The source impedance of amplifier A1 consists of the parallel connection of the hearing loop receive coil and a damping resistor of \(10k\Omega\). The hearing loop receiver has an integrating characteristic; its idealized gain has been determined as \(\frac{62.4\times 10^3}{s}\).

  1. Determine the show stopper value for the DIN-A weighted integrated noise at the output of the receive coil amplifier in Volts RMS.

  2. Determine the contribution of the receive coil and its termination resistor to this weighted output noise. The DIN-A weighting curve can be modeled as a transfer function see WiKi DIN-A weighting. Please download the SLiCAP script DIN_A.py.

  3. Consider the noise contribution of your feedback integrator circuit. Specify a budget for its noise contribution, and find a design limit (show-stopper) value for the resistance in this circuit.

  4. Determine possible values of the transconductance \(g_m\) and the input capacitance \(c_{iss}\) of a MOS that can be used as input stage of the receive coil amplifier. To this end, consider the MOS as the main noise contributer of the amplifier and model the noise behavior as shown below.

    The figure shows the use of an NMOS; it can be used for a PMOS changing the parameters

    https://analog-electronics.tudelft.nl/EE4109-2024-2025/designExample/HearingLoop/SLiCAP/img/noise_ciss_gm_N.svg
  5. Determine the values of the channel with \(W\), the channel length \(L\), and the quiescent operating current \(I_{DS}\) of a MOS using the results of the previous exercise and the SLiCAP EKV NMOS noise model NM18_noise and LTspice (SLiCAP) symbol SLM_noise.

  6. After all parameters have been defined, verify the noise with SLiCAP.

  7. Verify the result with LTspice.