# 28-11-2023: CS stage noise performance optimization#

Lecture: EE4109-5

Location: Pulse Hall 4

Time: 15:45 - 17:30

## Quiz#

## Design of CS stage noise behavior#

Stationary noise model of the CS stage

**Presentation**

The presentation Intrinsic CS stage: Stationary noise model presents the stationary noise model of a CS stage.

**Video**

Equivalent-input noise sources of a CS stage

**Presentation**

The presentation CS stage: Equivalent-input noise sources discusses the transformation of the channel noise into equivalent-input noise sources.

**Video**

EE4109 2020 4_2 Intrinsic CS stage: Equivalent-input noise sources

SLiCAP model of the equivalent-input noise sources of a CS stage

**Presentation**

The presentation CS stage: Equivalent-input noise sources - SLiCAP model presents the SLiCAP model of the equivalent-input noise sources of a CS stage.

**Video**

`EE4109 2020 4_3 Intrinsic CS stage: Equivalent-input noise sources SLiCAP model <https://youtu.be/-QyWqb6LNi8>_

CS stage: Noise optimization with a resistive source

**Presentation**

The presentation CS stage: Noise optimization with a resistive source shows the way in which the noise contribution of a CS stage can be minimized for a resistive source. LTspice examples ans SLiCAP examples are available.

Download SLiCAP-CSstage.zip and LTspice-CSstage.zip for running the analysis yourself.

**Videos**

CS stage: Noise optimization with a capacitive source

**Presentation**

The presentation "CS stage: Noise optimization with a capacitive source" shows the way in which the noise contribution of a CS stage can be minimized for a capacitive source.

**Video**

EE4109 2020 4_5 CS stage: Noise optimization with a capacitive voltage source

## Group exercise#

The source impedance of amplifier A1 consists of the parallel connection of the hearing loop receive coil and a damping resistor of 10 k:math:Omega. The hearing loop receiver has an integrating characteristic; its idealized gain has been determined as \(\frac{62.8\times 10^3}{s}\).

Determine the show stopper value for the integrated noise at the output of the receive coil amplifier.

Determine possible values of the transconductance \(g_m\) and the input capacitance \(c_{iss}\) of an NMOS that can be used as input stage of the receive coil amplifier. To this end, consider the MOS as the main noise contributer of the amplifier and model the noise behavior as shown below. (You can use SLiCAP for this purpose.)

Determine the values of the channel with \(W\), the channel length \(L\), and the quiescent operating current \(I_{DS}\) of the NMOS using the results of the previous exercise and the SLiCAP EKV NMOS model sub circuit CMOS18N and the LTspice (SLiCAP) symbol SLXM, or with the SLiCAP EKV NMOS noise model NM18_noise and LTspice (SLiCAP) symbol SLM_noise.

After all parameters have been defined, verify the noise with SLiCAP. For this purpose use the SLiCAP sub circuit NM18_noise and LTspice (SLiCAP) symbol SLM_noise.

Verify the result with LTspice.